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Shrink a BitVector that didn't mean to store bits for all physical registers.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123108 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
2011-01-09 03:45:44 +00:00
parent 4314268128
commit 00f93fc046
1 changed files with 4 additions and 6 deletions
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10
lib/CodeGen/TwoAddressInstructionPass.cpp
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@ -1016,8 +1016,7 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
<< MF.getFunction()->getName() << '\n'); << MF.getFunction()->getName() << '\n');
// ReMatRegs - Keep track of the registers whose def's are remat'ed. // ReMatRegs - Keep track of the registers whose def's are remat'ed.
BitVector ReMatRegs; BitVector ReMatRegs(MRI->getNumVirtRegs());
ReMatRegs.resize(MRI->getLastVirtReg()+1);
typedef DenseMap<unsigned, SmallVector<std::pair<unsigned, unsigned>, 4> > typedef DenseMap<unsigned, SmallVector<std::pair<unsigned, unsigned>, 4> >
TiedOperandMap; TiedOperandMap;
@ -1146,7 +1145,7 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
DEBUG(dbgs() << "2addr: REMATTING : " << *DefMI << "\n"); DEBUG(dbgs() << "2addr: REMATTING : " << *DefMI << "\n");
unsigned regASubIdx = mi->getOperand(DstIdx).getSubReg(); unsigned regASubIdx = mi->getOperand(DstIdx).getSubReg();
TII->reMaterialize(*mbbi, mi, regA, regASubIdx, DefMI, *TRI); TII->reMaterialize(*mbbi, mi, regA, regASubIdx, DefMI, *TRI);
ReMatRegs.set(regB); ReMatRegs.set(TargetRegisterInfo::virtReg2Index(regB));
++NumReMats; ++NumReMats;
} else { } else {
BuildMI(*mbbi, mi, mi->getDebugLoc(), TII->get(TargetOpcode::COPY), BuildMI(*mbbi, mi, mi->getDebugLoc(), TII->get(TargetOpcode::COPY),
@ -1232,13 +1231,12 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
} }
// Some remat'ed instructions are dead. // Some remat'ed instructions are dead.
int VReg = ReMatRegs.find_first(); for (int i = ReMatRegs.find_first(); i != -1; i = ReMatRegs.find_next(i)) {
while (VReg != -1) { unsigned VReg = TargetRegisterInfo::index2VirtReg(i);
if (MRI->use_nodbg_empty(VReg)) { if (MRI->use_nodbg_empty(VReg)) {
MachineInstr *DefMI = MRI->getVRegDef(VReg); MachineInstr *DefMI = MRI->getVRegDef(VReg);
DefMI->eraseFromParent(); DefMI->eraseFromParent();
} }
VReg = ReMatRegs.find_next(VReg);
} }
// Eliminate REG_SEQUENCE instructions. Their whole purpose was to preseve // Eliminate REG_SEQUENCE instructions. Their whole purpose was to preseve