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https://github.com/c64scene-ar/llvm-6502.git
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[Sparc]: Use cmp instruction instead of subcc to compare integers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183463 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1575,9 +1575,7 @@ static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) {
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// Get the condition flag.
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SDValue CompareFlag;
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if (LHS.getValueType().isInteger()) {
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EVT VTs[] = { LHS.getValueType(), MVT::Glue };
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SDValue Ops[2] = { LHS, RHS };
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CompareFlag = DAG.getNode(SPISD::CMPICC, dl, VTs, Ops, 2).getValue(1);
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CompareFlag = DAG.getNode(SPISD::CMPICC, dl, MVT::Glue, LHS, RHS);
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if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
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// 32-bit compares use the icc flags, 64-bit uses the xcc flags.
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Opc = LHS.getValueType() == MVT::i32 ? SPISD::BRICC : SPISD::BRXCC;
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@ -1605,10 +1603,7 @@ static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
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SDValue CompareFlag;
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if (LHS.getValueType().isInteger()) {
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// subcc returns a value
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EVT VTs[] = { LHS.getValueType(), MVT::Glue };
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SDValue Ops[2] = { LHS, RHS };
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CompareFlag = DAG.getNode(SPISD::CMPICC, dl, VTs, Ops, 2).getValue(1);
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CompareFlag = DAG.getNode(SPISD::CMPICC, dl, MVT::Glue, LHS, RHS);
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Opc = LHS.getValueType() == MVT::i32 ?
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SPISD::SELECT_ICC : SPISD::SELECT_XCC;
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if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
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@ -160,7 +160,7 @@ def : Pat<(sube i64:$a, i64:$b), (SUBXrr $a, $b)>;
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def : Pat<(addc i64:$a, i64:$b), (ADDCCrr $a, $b)>;
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def : Pat<(subc i64:$a, i64:$b), (SUBCCrr $a, $b)>;
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def : Pat<(SPcmpicc i64:$a, i64:$b), (SUBCCrr $a, $b)>;
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def : Pat<(SPcmpicc i64:$a, i64:$b), (CMPrr $a, $b)>;
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// Register-immediate instructions.
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@ -171,7 +171,7 @@ def : Pat<(xor i64:$a, (i64 simm13:$b)), (XORri $a, (as_i32imm $b))>;
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def : Pat<(add i64:$a, (i64 simm13:$b)), (ADDri $a, (as_i32imm $b))>;
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def : Pat<(sub i64:$a, (i64 simm13:$b)), (SUBri $a, (as_i32imm $b))>;
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def : Pat<(SPcmpicc i64:$a, (i64 simm13:$b)), (SUBCCri $a, (as_i32imm $b))>;
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def : Pat<(SPcmpicc i64:$a, (i64 simm13:$b)), (CMPri $a, (as_i32imm $b))>;
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} // Predicates = [Is64Bit]
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@ -89,6 +89,8 @@ def calltarget : Operand<i32>;
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let PrintMethod = "printCCOperand" in
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def CCOp : Operand<i32>;
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def SDTSPcmpicc :
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SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
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def SDTSPcmpfcc :
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SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisSameAs<0, 1>]>;
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def SDTSPbrcc :
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@ -100,7 +102,7 @@ SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
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def SDTSPITOF :
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SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
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def SPcmpicc : SDNode<"SPISD::CMPICC", SDTIntBinOp, [SDNPOutGlue]>;
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def SPcmpicc : SDNode<"SPISD::CMPICC", SDTSPcmpicc, [SDNPOutGlue]>;
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def SPcmpfcc : SDNode<"SPISD::CMPFCC", SDTSPcmpfcc, [SDNPOutGlue]>;
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def SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
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def SPbrxcc : SDNode<"SPISD::BRXCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
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@ -476,8 +478,18 @@ defm SUB : F3_12 <"sub" , 0b000100, sub>;
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let Uses = [ICC] in
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defm SUBX : F3_12 <"subx" , 0b001100, sube>;
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let Defs = [ICC] in
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defm SUBCC : F3_12 <"subcc", 0b010100, SPcmpicc>;
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let Defs = [ICC] in {
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defm SUBCC : F3_12 <"subcc", 0b010100, subc>;
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def CMPrr : F3_1<2, 0b010100,
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(outs), (ins IntRegs:$b, IntRegs:$c),
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"cmp $b, $c",
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[(SPcmpicc i32:$b, i32:$c)]>;
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def CMPri : F3_1<2, 0b010100,
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(outs), (ins IntRegs:$b, i32imm:$c),
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"cmp $b, $c",
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[(SPcmpicc i32:$b, (i32 simm13:$c))]>;
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}
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let Uses = [ICC], Defs = [ICC] in
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def SUBXCCrr: F3_1<2, 0b011100,
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@ -795,11 +807,6 @@ def : Pat<(i32 simm13:$val),
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def : Pat<(i32 imm:$val),
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(ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
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// subc
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def : Pat<(subc i32:$b, i32:$c),
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(SUBCCrr $b, $c)>;
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def : Pat<(subc i32:$b, simm13:$val),
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(SUBCCri $b, imm:$val)>;
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// Global addresses, constant pool entries
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def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>;
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@ -21,10 +21,10 @@ entry:
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define i32 @test_select_int_icc(i32 %a, i32 %b, i32 %c) nounwind readnone noinline {
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entry:
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; V8: test_select_int_icc
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; V8: subcc
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; V8: cmp
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; V8: {{be|bne}}
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; V9: test_select_int_icc
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; V9: subcc
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; V9: cmp
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; V9-NOT: {{be|bne}}
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; V9: mov{{e|ne}} %icc
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%0 = icmp eq i32 %a, 0
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@ -36,10 +36,10 @@ entry:
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define float @test_select_fp_icc(i32 %a, float %f1, float %f2) nounwind readnone noinline {
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entry:
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; V8: test_select_fp_icc
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; V8: subcc
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; V8: cmp
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; V8: {{be|bne}}
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; V9: test_select_fp_icc
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; V9: subcc
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; V9: cmp
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; V9-NOT: {{be|bne}}
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; V9: fmovs{{e|ne}} %icc
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%0 = icmp eq i32 %a, 0
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@ -50,10 +50,10 @@ entry:
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define double @test_select_dfp_icc(i32 %a, double %f1, double %f2) nounwind readnone noinline {
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entry:
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; V8: test_select_dfp_icc
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; V8: subcc
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; V8: cmp
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; V8: {{be|bne}}
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; V9: test_select_dfp_icc
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; V9: subcc
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; V9: cmp
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; V9-NOT: {{be|bne}}
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; V9: fmovd{{e|ne}} %icc
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%0 = icmp eq i32 %a, 0
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@ -40,7 +40,7 @@ bb: ; preds = %entry, %bb
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%a_addr.0 = add i32 %.pn, %a_addr.18
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%3 = add nsw i32 %1, 1
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%exitcond = icmp eq i32 %3, %b
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;CHECK: subcc
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;CHECK: cmp
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;CHECK: bne
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;CHECK-NOT: nop
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br i1 %exitcond, label %bb5, label %bb
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@ -57,7 +57,7 @@ entry:
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;CHECK: test_inlineasm
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;CHECK: sethi
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;CHECK: !NO_APP
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;CHECK-NEXT: subcc
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;CHECK-NEXT: cmp
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;CHECK-NEXT: bg
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;CHECK-NEXT: nop
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tail call void asm sideeffect "sethi 0, %g0", ""() nounwind
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@ -230,7 +230,7 @@ entry:
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declare void @g(i8*)
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; CHECK: expand_setcc
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; CHECK: subcc %i0, 1,
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; CHECK: cmp %i0, 1
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; CHECK: movl %xcc, 1,
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define i32 @expand_setcc(i64 %a) {
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%cond = icmp sle i64 %a, 0
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@ -2,7 +2,7 @@
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; Testing 64-bit conditionals. The sparc64 triple is an alias for sparcv9.
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; CHECK: cmpri
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; CHECK: subcc %i1, 1
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; CHECK: cmp %i1, 1
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; CHECK: bpe %xcc,
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define void @cmpri(i64* %p, i64 %x) {
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entry:
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@ -18,7 +18,7 @@ if.end:
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}
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; CHECK: cmprr
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; CHECK: subcc %i1, %i2
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; CHECK: cmp %i1, %i2
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; CHECK: bpgu %xcc,
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define void @cmprr(i64* %p, i64 %x, i64 %y) {
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entry:
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@ -34,7 +34,7 @@ if.end:
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}
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; CHECK: selecti32_xcc
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; CHECK: subcc %i0, %i1
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; CHECK: cmp %i0, %i1
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; CHECK: movg %xcc, %i2, %i3
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; CHECK: restore %g0, %i3, %o0
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define i32 @selecti32_xcc(i64 %x, i64 %y, i32 %a, i32 %b) {
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@ -45,7 +45,7 @@ entry:
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}
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; CHECK: selecti64_xcc
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; CHECK: subcc %i0, %i1
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; CHECK: cmp %i0, %i1
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; CHECK: movg %xcc, %i2, %i3
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; CHECK: restore %g0, %i3, %o0
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define i64 @selecti64_xcc(i64 %x, i64 %y, i64 %a, i64 %b) {
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@ -56,7 +56,7 @@ entry:
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}
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; CHECK: selecti64_icc
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; CHECK: subcc %i0, %i1
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; CHECK: cmp %i0, %i1
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; CHECK: movg %icc, %i2, %i3
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; CHECK: restore %g0, %i3, %o0
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define i64 @selecti64_icc(i32 %x, i32 %y, i64 %a, i64 %b) {
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@ -78,7 +78,7 @@ entry:
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}
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; CHECK: selectf32_xcc
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; CHECK: subcc %i0, %i1
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; CHECK: cmp %i0, %i1
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; CHECK: fmovsg %xcc, %f5, %f7
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; CHECK: fmovs %f7, %f1
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define float @selectf32_xcc(i64 %x, i64 %y, float %a, float %b) {
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@ -89,7 +89,7 @@ entry:
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}
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; CHECK: selectf64_xcc
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; CHECK: subcc %i0, %i1
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; CHECK: cmp %i0, %i1
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; CHECK: fmovdg %xcc, %f4, %f6
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; CHECK: fmovd %f6, %f0
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define double @selectf64_xcc(i64 %x, i64 %y, double %a, double %b) {
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@ -101,7 +101,7 @@ entry:
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; The MOVXCC instruction can't use %g0 for its tied operand.
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; CHECK: select_consti64_xcc
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; CHECK: subcc
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; CHECK: cmp
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; CHECK: movg %xcc, 123, %i0
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define i64 @select_consti64_xcc(i64 %x, i64 %y) {
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entry:
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