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R600/SI: Match integer min / max instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222015 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault
parent
8fd3b90c3f
commit
01213b1132
@ -1000,19 +1000,14 @@ SDValue AMDGPUTargetLowering::LowerIntrinsicLRP(SDValue Op,
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}
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/// \brief Generate Min/Max node
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SDValue AMDGPUTargetLowering::CombineMinMax(SDLoc DL,
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EVT VT,
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SDValue LHS,
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SDValue RHS,
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SDValue True,
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SDValue False,
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SDValue CC,
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SelectionDAG &DAG) const {
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if (VT != MVT::f32 &&
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(VT != MVT::f64 ||
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Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS))
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return SDValue();
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SDValue AMDGPUTargetLowering::CombineFMinMax(SDLoc DL,
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EVT VT,
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SDValue LHS,
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SDValue RHS,
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SDValue True,
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SDValue False,
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SDValue CC,
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SelectionDAG &DAG) const {
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if (!(LHS == True && RHS == False) && !(LHS == False && RHS == True))
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return SDValue();
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@ -1057,6 +1052,45 @@ SDValue AMDGPUTargetLowering::CombineMinMax(SDLoc DL,
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return SDValue();
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}
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/// \brief Generate Min/Max node
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SDValue AMDGPUTargetLowering::CombineIMinMax(SDLoc DL,
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EVT VT,
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SDValue LHS,
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SDValue RHS,
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SDValue True,
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SDValue False,
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SDValue CC,
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SelectionDAG &DAG) const {
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if (!(LHS == True && RHS == False) && !(LHS == False && RHS == True))
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return SDValue();
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ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
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switch (CCOpcode) {
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case ISD::SETULE:
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case ISD::SETULT: {
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unsigned Opc = (LHS == True) ? AMDGPUISD::UMIN : AMDGPUISD::UMAX;
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return DAG.getNode(Opc, DL, VT, LHS, RHS);
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}
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case ISD::SETLE:
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case ISD::SETLT: {
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unsigned Opc = (LHS == True) ? AMDGPUISD::SMIN : AMDGPUISD::SMAX;
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return DAG.getNode(Opc, DL, VT, LHS, RHS);
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}
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case ISD::SETGT:
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case ISD::SETGE: {
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unsigned Opc = (LHS == True) ? AMDGPUISD::SMAX : AMDGPUISD::SMIN;
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return DAG.getNode(Opc, DL, VT, LHS, RHS);
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}
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case ISD::SETUGE:
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case ISD::SETUGT: {
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unsigned Opc = (LHS == True) ? AMDGPUISD::UMAX : AMDGPUISD::UMIN;
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return DAG.getNode(Opc, DL, VT, LHS, RHS);
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}
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default:
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return SDValue();
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}
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}
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SDValue AMDGPUTargetLowering::ScalarizeVectorLoad(const SDValue Op,
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SelectionDAG &DAG) const {
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LoadSDNode *Load = cast<LoadSDNode>(Op);
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@ -2117,20 +2151,25 @@ SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
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SDLoc DL(N);
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EVT VT = N->getValueType(0);
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SDValue LHS = N->getOperand(0);
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SDValue RHS = N->getOperand(1);
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SDValue True = N->getOperand(2);
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SDValue False = N->getOperand(3);
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SDValue CC = N->getOperand(4);
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if (VT == MVT::f32 ||
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(VT == MVT::f64 &&
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Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)) {
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SDValue LHS = N->getOperand(0);
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SDValue RHS = N->getOperand(1);
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SDValue True = N->getOperand(2);
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SDValue False = N->getOperand(3);
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SDValue CC = N->getOperand(4);
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return CombineMinMax(DL, VT, LHS, RHS, True, False, CC, DAG);
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return CombineFMinMax(DL, VT, LHS, RHS, True, False, CC, DAG);
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}
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break;
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}
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case ISD::SELECT: {
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SDValue Cond = N->getOperand(0);
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if (Cond.getOpcode() == ISD::SETCC) {
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SDLoc DL(N);
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EVT VT = N->getValueType(0);
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SDValue LHS = Cond.getOperand(0);
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SDValue RHS = Cond.getOperand(1);
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SDValue CC = Cond.getOperand(2);
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@ -2138,8 +2177,17 @@ SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
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SDValue True = N->getOperand(1);
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SDValue False = N->getOperand(2);
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if (VT == MVT::f32 ||
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(VT == MVT::f64 &&
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Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)) {
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return CombineFMinMax(DL, VT, LHS, RHS, True, False, CC, DAG);
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}
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return CombineMinMax(DL, VT, LHS, RHS, True, False, CC, DAG);
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// TODO: Implement min / max Evergreen instructions.
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if (VT == MVT::i32 &&
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Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
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return CombineIMinMax(DL, VT, LHS, RHS, True, False, CC, DAG);
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}
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}
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break;
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@ -140,14 +140,23 @@ public:
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SDValue LowerIntrinsicIABS(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerIntrinsicLRP(SDValue Op, SelectionDAG &DAG) const;
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SDValue CombineMinMax(SDLoc DL,
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EVT VT,
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SDValue LHS,
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SDValue RHS,
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SDValue True,
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SDValue False,
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SDValue CC,
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SelectionDAG &DAG) const;
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SDValue CombineFMinMax(SDLoc DL,
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EVT VT,
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SDValue LHS,
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SDValue RHS,
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SDValue True,
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SDValue False,
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SDValue CC,
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SelectionDAG &DAG) const;
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SDValue CombineIMinMax(SDLoc DL,
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EVT VT,
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SDValue LHS,
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SDValue RHS,
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SDValue True,
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SDValue False,
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SDValue CC,
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SelectionDAG &DAG) const;
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const char* getTargetNodeName(unsigned Opcode) const override;
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virtual SDNode *PostISelFolding(MachineSDNode *N,
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99
test/CodeGen/R600/max.ll
Normal file
99
test/CodeGen/R600/max.ll
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@ -0,0 +1,99 @@
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; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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declare i32 @llvm.r600.read.tidig.x() nounwind readnone
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; FUNC-LABEL: @v_test_imax_sge_i32
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; SI: v_max_i32_e32
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define void @v_test_imax_sge_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr) nounwind {
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%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%gep0 = getelementptr i32 addrspace(1)* %aptr, i32 %tid
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%gep1 = getelementptr i32 addrspace(1)* %bptr, i32 %tid
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%outgep = getelementptr i32 addrspace(1)* %out, i32 %tid
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%a = load i32 addrspace(1)* %gep0, align 4
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%b = load i32 addrspace(1)* %gep1, align 4
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%cmp = icmp sge i32 %a, %b
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%val = select i1 %cmp, i32 %a, i32 %b
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store i32 %val, i32 addrspace(1)* %outgep, align 4
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ret void
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}
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; FUNC-LABEL: @s_test_imax_sge_i32
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; SI: s_max_i32
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define void @s_test_imax_sge_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
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%cmp = icmp sge i32 %a, %b
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%val = select i1 %cmp, i32 %a, i32 %b
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store i32 %val, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: @v_test_imax_sgt_i32
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; SI: v_max_i32_e32
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define void @v_test_imax_sgt_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr) nounwind {
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%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%gep0 = getelementptr i32 addrspace(1)* %aptr, i32 %tid
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%gep1 = getelementptr i32 addrspace(1)* %bptr, i32 %tid
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%outgep = getelementptr i32 addrspace(1)* %out, i32 %tid
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%a = load i32 addrspace(1)* %gep0, align 4
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%b = load i32 addrspace(1)* %gep1, align 4
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%cmp = icmp sgt i32 %a, %b
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%val = select i1 %cmp, i32 %a, i32 %b
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store i32 %val, i32 addrspace(1)* %outgep, align 4
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ret void
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}
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; FUNC-LABEL: @s_test_imax_sgt_i32
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; SI: s_max_i32
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define void @s_test_imax_sgt_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
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%cmp = icmp sgt i32 %a, %b
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%val = select i1 %cmp, i32 %a, i32 %b
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store i32 %val, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: @v_test_umax_uge_i32
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; SI: v_max_u32_e32
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define void @v_test_umax_uge_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr) nounwind {
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%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%gep0 = getelementptr i32 addrspace(1)* %aptr, i32 %tid
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%gep1 = getelementptr i32 addrspace(1)* %bptr, i32 %tid
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%outgep = getelementptr i32 addrspace(1)* %out, i32 %tid
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%a = load i32 addrspace(1)* %gep0, align 4
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%b = load i32 addrspace(1)* %gep1, align 4
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%cmp = icmp uge i32 %a, %b
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%val = select i1 %cmp, i32 %a, i32 %b
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store i32 %val, i32 addrspace(1)* %outgep, align 4
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ret void
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}
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; FUNC-LABEL: @s_test_umax_uge_i32
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; SI: s_max_u32
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define void @s_test_umax_uge_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
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%cmp = icmp uge i32 %a, %b
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%val = select i1 %cmp, i32 %a, i32 %b
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store i32 %val, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: @v_test_umax_ugt_i32
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; SI: v_max_u32_e32
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define void @v_test_umax_ugt_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr) nounwind {
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%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%gep0 = getelementptr i32 addrspace(1)* %aptr, i32 %tid
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%gep1 = getelementptr i32 addrspace(1)* %bptr, i32 %tid
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%outgep = getelementptr i32 addrspace(1)* %out, i32 %tid
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%a = load i32 addrspace(1)* %gep0, align 4
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%b = load i32 addrspace(1)* %gep1, align 4
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%cmp = icmp ugt i32 %a, %b
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%val = select i1 %cmp, i32 %a, i32 %b
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store i32 %val, i32 addrspace(1)* %outgep, align 4
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ret void
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}
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; FUNC-LABEL: @s_test_umax_ugt_i32
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; SI: s_max_u32
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define void @s_test_umax_ugt_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
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%cmp = icmp ugt i32 %a, %b
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%val = select i1 %cmp, i32 %a, i32 %b
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store i32 %val, i32 addrspace(1)* %out, align 4
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ret void
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}
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99
test/CodeGen/R600/min.ll
Normal file
99
test/CodeGen/R600/min.ll
Normal file
@ -0,0 +1,99 @@
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; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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declare i32 @llvm.r600.read.tidig.x() nounwind readnone
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; FUNC-LABEL: @v_test_imin_sle_i32
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; SI: v_min_i32_e32
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define void @v_test_imin_sle_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr) nounwind {
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%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%gep0 = getelementptr i32 addrspace(1)* %aptr, i32 %tid
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%gep1 = getelementptr i32 addrspace(1)* %bptr, i32 %tid
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%outgep = getelementptr i32 addrspace(1)* %out, i32 %tid
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%a = load i32 addrspace(1)* %gep0, align 4
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%b = load i32 addrspace(1)* %gep1, align 4
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%cmp = icmp sle i32 %a, %b
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%val = select i1 %cmp, i32 %a, i32 %b
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store i32 %val, i32 addrspace(1)* %outgep, align 4
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ret void
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}
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; FUNC-LABEL: @s_test_imin_sle_i32
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; SI: s_min_i32
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define void @s_test_imin_sle_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
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%cmp = icmp sle i32 %a, %b
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%val = select i1 %cmp, i32 %a, i32 %b
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store i32 %val, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: @v_test_imin_slt_i32
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; SI: v_min_i32_e32
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define void @v_test_imin_slt_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr) nounwind {
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%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%gep0 = getelementptr i32 addrspace(1)* %aptr, i32 %tid
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%gep1 = getelementptr i32 addrspace(1)* %bptr, i32 %tid
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%outgep = getelementptr i32 addrspace(1)* %out, i32 %tid
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%a = load i32 addrspace(1)* %gep0, align 4
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%b = load i32 addrspace(1)* %gep1, align 4
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%cmp = icmp slt i32 %a, %b
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%val = select i1 %cmp, i32 %a, i32 %b
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store i32 %val, i32 addrspace(1)* %outgep, align 4
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ret void
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}
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; FUNC-LABEL: @s_test_imin_slt_i32
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; SI: s_min_i32
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define void @s_test_imin_slt_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
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%cmp = icmp slt i32 %a, %b
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%val = select i1 %cmp, i32 %a, i32 %b
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store i32 %val, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: @v_test_umin_ule_i32
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; SI: v_min_u32_e32
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define void @v_test_umin_ule_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr) nounwind {
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%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%gep0 = getelementptr i32 addrspace(1)* %aptr, i32 %tid
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%gep1 = getelementptr i32 addrspace(1)* %bptr, i32 %tid
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%outgep = getelementptr i32 addrspace(1)* %out, i32 %tid
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%a = load i32 addrspace(1)* %gep0, align 4
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%b = load i32 addrspace(1)* %gep1, align 4
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%cmp = icmp ule i32 %a, %b
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%val = select i1 %cmp, i32 %a, i32 %b
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store i32 %val, i32 addrspace(1)* %outgep, align 4
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ret void
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}
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; FUNC-LABEL: @s_test_umin_ule_i32
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; SI: s_min_u32
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define void @s_test_umin_ule_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
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%cmp = icmp ule i32 %a, %b
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%val = select i1 %cmp, i32 %a, i32 %b
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store i32 %val, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: @v_test_umin_ult_i32
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; SI: v_min_u32_e32
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define void @v_test_umin_ult_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr) nounwind {
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%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%gep0 = getelementptr i32 addrspace(1)* %aptr, i32 %tid
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%gep1 = getelementptr i32 addrspace(1)* %bptr, i32 %tid
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%outgep = getelementptr i32 addrspace(1)* %out, i32 %tid
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%a = load i32 addrspace(1)* %gep0, align 4
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%b = load i32 addrspace(1)* %gep1, align 4
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%cmp = icmp ult i32 %a, %b
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%val = select i1 %cmp, i32 %a, i32 %b
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store i32 %val, i32 addrspace(1)* %outgep, align 4
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ret void
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}
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; FUNC-LABEL: @s_test_umin_ult_i32
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; SI: s_min_u32
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define void @s_test_umin_ult_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
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%cmp = icmp ult i32 %a, %b
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%val = select i1 %cmp, i32 %a, i32 %b
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store i32 %val, i32 addrspace(1)* %out, align 4
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ret void
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}
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