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[PowerPC] Support select-cc for VSX
The tests test/CodeGen/Generic/select-cc.ll and test/CodeGen/PowerPC/select-cc.ll both fail with VSX enabled. The problem is that the lowering logic for the SELECT and SELECT_CC operations doesn't currently support the VSX registers. This patch fixes that. In lib/Target/PowerPC/PPCInstrInfo.td, we have pseudos to handle this for other register classes. Similar pseudos are added in PPCInstrVSX.td (they must be there, because the "vsrc" register class definition appears there) for the VSRC register class. The SELECT_VSRC pseudo is then used in pattern matching for SELECT_CC. The rest of the patch just adds logic for SELECT_VSRC wherever similar logic appears for SELECT_VRRC. There are no new test cases because the existing tests above test this, along with a variant in test/CodeGen/PowerPC/vsx.ll. After discussion with Hal, a future patch will add similar _VSFRC variants to override f64 type handling (currently using F8RC). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220385 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1323,6 +1323,9 @@ SDNode *PPCDAGToDAGISel::Select(SDNode *N) {
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SelectCCOp = PPC::SELECT_CC_F4;
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else if (N->getValueType(0) == MVT::f64)
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SelectCCOp = PPC::SELECT_CC_F8;
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else if (N->getValueType(0) == MVT::v2f64 ||
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N->getValueType(0) == MVT::v2i64)
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SelectCCOp = PPC::SELECT_CC_VSRC;
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else
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SelectCCOp = PPC::SELECT_CC_VRRC;
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@ -1686,7 +1689,8 @@ void PPCDAGToDAGISel::PeepholeCROps() {
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case PPC::SELECT_I8:
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case PPC::SELECT_F4:
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case PPC::SELECT_F8:
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case PPC::SELECT_VRRC: {
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case PPC::SELECT_VRRC:
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case PPC::SELECT_VSRC: {
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SDValue Op = MachineNode->getOperand(0);
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if (Op.isMachineOpcode()) {
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if (Op.getMachineOpcode() == PPC::CRSET)
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@ -1992,6 +1996,7 @@ void PPCDAGToDAGISel::PeepholeCROps() {
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case PPC::SELECT_F4:
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case PPC::SELECT_F8:
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case PPC::SELECT_VRRC:
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case PPC::SELECT_VSRC:
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if (Op1Set)
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ResNode = MachineNode->getOperand(1).getNode();
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else if (Op1Unset)
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@ -7062,11 +7062,13 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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MI->getOpcode() == PPC::SELECT_CC_F4 ||
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MI->getOpcode() == PPC::SELECT_CC_F8 ||
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MI->getOpcode() == PPC::SELECT_CC_VRRC ||
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MI->getOpcode() == PPC::SELECT_CC_VSRC ||
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MI->getOpcode() == PPC::SELECT_I4 ||
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MI->getOpcode() == PPC::SELECT_I8 ||
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MI->getOpcode() == PPC::SELECT_F4 ||
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MI->getOpcode() == PPC::SELECT_F8 ||
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MI->getOpcode() == PPC::SELECT_VRRC) {
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MI->getOpcode() == PPC::SELECT_VRRC ||
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MI->getOpcode() == PPC::SELECT_VSRC) {
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// The incoming instruction knows the destination vreg to set, the
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// condition code register to branch on, the true/false values to
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// select between, and a branch opcode to use.
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@ -7097,7 +7099,8 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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MI->getOpcode() == PPC::SELECT_I8 ||
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MI->getOpcode() == PPC::SELECT_F4 ||
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MI->getOpcode() == PPC::SELECT_F8 ||
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MI->getOpcode() == PPC::SELECT_VRRC) {
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MI->getOpcode() == PPC::SELECT_VRRC ||
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MI->getOpcode() == PPC::SELECT_VSRC) {
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BuildMI(BB, dl, TII->get(PPC::BC))
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.addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
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} else {
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@ -719,6 +719,21 @@ let Uses = [RM] in {
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} // neverHasSideEffects
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} // AddedComplexity
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// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
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// instruction selection into a branch sequence.
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let usesCustomInserter = 1, // Expanded after instruction selection.
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PPC970_Single = 1 in {
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def SELECT_CC_VSRC: Pseudo<(outs vsrc:$dst),
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(ins crrc:$cond, vsrc:$T, vsrc:$F, i32imm:$BROPC),
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"#SELECT_CC_VSRC",
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[]>;
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def SELECT_VSRC: Pseudo<(outs vsrc:$dst), (ins crbitrc:$cond,
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vsrc:$T, vsrc:$F), "#SELECT_VSRC",
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[(set v2f64:$dst,
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(select i1:$cond, v2f64:$T, v2f64:$F))]>;
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}
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def : InstAlias<"xvmovdp $XT, $XB",
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(XVCPSGNDP vsrc:$XT, vsrc:$XB, vsrc:$XB)>;
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def : InstAlias<"xvmovsp $XT, $XB",
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@ -820,6 +835,20 @@ def : Pat<(v4i32 (load xoaddr:$src)), (LXVW4X xoaddr:$src)>;
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def : Pat<(store v4i32:$rS, xoaddr:$dst),
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(STXVW4X $rS, xoaddr:$dst)>;
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// Selects.
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def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETLT)),
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(SELECT_VSRC (CRANDC $rhs, $lhs), $tval, $fval)>;
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def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETLE)),
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(SELECT_VSRC (CRORC $rhs, $lhs), $tval, $fval)>;
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def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETEQ)),
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(SELECT_VSRC (CREQV $lhs, $rhs), $tval, $fval)>;
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def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETGE)),
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(SELECT_VSRC (CRORC $lhs, $rhs), $tval, $fval)>;
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def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETGT)),
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(SELECT_VSRC (CRANDC $lhs, $rhs), $tval, $fval)>;
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def : Pat<(v2f64 (selectcc i1:$lhs, i1:$rhs, v2f64:$tval, v2f64:$fval, SETNE)),
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(SELECT_VSRC (CRXOR $lhs, $rhs), $tval, $fval)>;
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} // AddedComplexity
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} // HasVSX
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