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Remove the need to cache the subtarget in the Sparc TargetRegisterInfo

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classes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232013 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher
2015-03-12 05:55:26 +00:00
parent ae02704ac7
commit 013ed4aa69
4 changed files with 11 additions and 12 deletions
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5
lib/Target/Sparc/SparcInstrInfo.cpp
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@@ -33,9 +33,8 @@ using namespace llvm;
void SparcInstrInfo::anchor() {}
SparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST)
: SparcGenInstrInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
RI(ST), Subtarget(ST) {
}
: SparcGenInstrInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP), RI(),
Subtarget(ST) {}
/// isLoadFromStackSlot - If the specified machine instruction is a direct
/// load from a stack slot, return the virtual or physical register number of