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Use a custom expander for all FP to int conversions, as the X86 only has
FP-to-int-in-memory: this exposes the load from the stored slot to the selection dag, allowing it to be folded into other operaions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22556 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -59,6 +59,8 @@ namespace {
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/// to the X86::FIST*m instructions and the rounding mode change stuff. It
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/// has two inputs (token chain and address) and two outputs (FP value and
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/// token chain).
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FP_TO_INT16_IN_MEM,
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FP_TO_INT32_IN_MEM,
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FP_TO_INT64_IN_MEM,
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/// CALL/TAILCALL - These operations represent an abstract X86 call
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@ -130,6 +132,8 @@ namespace {
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// isn't legal.
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setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
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setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
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setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
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setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
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}
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// Handle FP_TO_UINT by promoting the destination to a larger signed
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@ -987,24 +991,34 @@ SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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return DAG.getNode(X86ISD::FILD64m, RTs, Ops);
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}
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case ISD::FP_TO_SINT: {
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assert(Op.getValueType() == MVT::i64 &&
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assert(Op.getValueType() <= MVT::i64 && Op.getValueType() >= MVT::i16 &&
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Op.getOperand(0).getValueType() == MVT::f64 &&
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"Unknown FP_TO_SINT to lower!");
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// We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
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// stack slot.
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MachineFunction &MF = DAG.getMachineFunction();
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int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
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unsigned MemSize = MVT::getSizeInBits(Op.getValueType())/8;
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int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
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SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
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// Build the FISTP64
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unsigned Opc;
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switch (Op.getValueType()) {
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default: assert(0 && "Invalid FP_TO_SINT to lower!");
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case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
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case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
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case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
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}
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// Build the FP_TO_INT*_IN_MEM
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std::vector<SDOperand> Ops;
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Ops.push_back(DAG.getEntryNode());
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Ops.push_back(Op.getOperand(0));
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Ops.push_back(StackSlot);
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SDOperand FIST = DAG.getNode(X86ISD::FP_TO_INT64_IN_MEM, MVT::Other, Ops);
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SDOperand FIST = DAG.getNode(Opc, MVT::Other, Ops);
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// Load the result.
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return DAG.getLoad(MVT::i64, FIST, StackSlot, DAG.getSrcValue(NULL));
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return DAG.getLoad(Op.getValueType(), FIST, StackSlot,
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DAG.getSrcValue(NULL));
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}
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}
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}
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@ -2449,13 +2463,13 @@ unsigned ISel::SelectExpr(SDOperand N) {
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}
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return Result;
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}
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case ISD::FP_TO_SINT: {
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case ISD::FP_TO_SINT:
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Tmp1 = SelectExpr(N.getOperand(0)); // Get the operand register
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// If the target supports SSE2 and is performing FP operations in SSE regs
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// instead of the FP stack, then we can use the efficient CVTSS2SI and
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// CVTSD2SI instructions.
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if (X86ScalarSSE) {
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assert(X86ScalarSSE);
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if (MVT::f32 == N.getOperand(0).getValueType()) {
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BuildMI(BB, X86::CVTTSS2SIrr, 1, Result).addReg(Tmp1);
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} else if (MVT::f64 == N.getOperand(0).getValueType()) {
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@ -2465,60 +2479,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
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abort();
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}
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return Result;
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}
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// Change the floating point control register to use "round towards zero"
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// mode when truncating to an integer value.
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//
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MachineFunction *F = BB->getParent();
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int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
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addFrameReference(BuildMI(BB, X86::FNSTCW16m, 4), CWFrameIdx);
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// Load the old value of the high byte of the control word...
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unsigned HighPartOfCW = MakeReg(MVT::i8);
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addFrameReference(BuildMI(BB, X86::MOV8rm, 4, HighPartOfCW),
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CWFrameIdx, 1);
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// Set the high part to be round to zero...
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addFrameReference(BuildMI(BB, X86::MOV8mi, 5),
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CWFrameIdx, 1).addImm(12);
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// Reload the modified control word now...
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addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx);
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// Restore the memory image of control word to original value
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addFrameReference(BuildMI(BB, X86::MOV8mr, 5),
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CWFrameIdx, 1).addReg(HighPartOfCW);
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// Spill the integer to memory and reload it from there.
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unsigned Size = MVT::getSizeInBits(Node->getValueType(0))/8;
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int FrameIdx = F->getFrameInfo()->CreateStackObject(Size, Size);
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switch (Node->getValueType(0)) {
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default: assert(0 && "Unsupported store class!");
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case MVT::i16:
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addFrameReference(BuildMI(BB, X86::FIST16m, 5), FrameIdx).addReg(Tmp1);
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break;
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case MVT::i32:
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addFrameReference(BuildMI(BB, X86::FIST32m, 5), FrameIdx).addReg(Tmp1);
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break;
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}
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switch (Node->getValueType(0)) {
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default:
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assert(0 && "Unknown integer type!");
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case MVT::i32:
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addFrameReference(BuildMI(BB, X86::MOV32rm, 4, Result), FrameIdx);
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break;
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case MVT::i16:
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addFrameReference(BuildMI(BB, X86::MOV16rm, 4, Result), FrameIdx);
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break;
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}
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// Reload the original control word now.
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addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx);
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return Result;
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}
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case ISD::ADD:
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Op0 = N.getOperand(0);
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Op1 = N.getOperand(1);
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@ -4347,6 +4308,8 @@ void ISel::Select(SDOperand N) {
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SelectExpr(N.getValue(0));
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return;
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case X86ISD::FP_TO_INT16_IN_MEM:
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case X86ISD::FP_TO_INT32_IN_MEM:
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case X86ISD::FP_TO_INT64_IN_MEM: {
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assert(N.getOperand(1).getValueType() == MVT::f64);
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X86AddressMode AM;
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@ -4384,7 +4347,14 @@ void ISel::Select(SDOperand N) {
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addFrameReference(BuildMI(BB, X86::MOV8mr, 5),
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CWFrameIdx, 1).addReg(HighPartOfCW);
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addFullAddress(BuildMI(BB, X86::FISTP64m, 5), AM).addReg(ValReg);
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// Get the X86 opcode to use.
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switch (N.getOpcode()) {
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case X86ISD::FP_TO_INT16_IN_MEM: Tmp1 = X86::FIST16m; break;
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case X86ISD::FP_TO_INT32_IN_MEM: Tmp1 = X86::FIST32m; break;
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case X86ISD::FP_TO_INT64_IN_MEM: Tmp1 = X86::FISTP64m; break;
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}
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addFullAddress(BuildMI(BB, Tmp1, 5), AM).addReg(ValReg);
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// Reload the original control word now.
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addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx);
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