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Small tweaks noticed while on the plane.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24492 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -556,6 +556,8 @@ class VAForm_1<bits<6> xo, dag OL, string asmstr,
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bits<5> VA;
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bits<5> VB;
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bits<5> VC;
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let Pattern = pattern;
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let Inst{6-10} = VD;
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let Inst{11-15} = VA;
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@ -572,6 +574,8 @@ class VXForm_1<bits<11> xo, dag OL, string asmstr,
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bits<5> VA;
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bits<5> VB;
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let Pattern = pattern;
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let Inst{6-10} = VD;
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let Inst{11-15} = VA;
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let Inst{16-20} = VB;
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@ -586,6 +590,8 @@ class VXRForm_1<bits<10> xo, bit rc, dag OL, string asmstr,
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bits<5> VA;
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bits<5> VB;
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let Pattern = pattern;
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let Inst{6-10} = VD;
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let Inst{11-15} = VA;
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let Inst{16-20} = VB;
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@ -464,9 +464,9 @@ def EXTSB : XForm_11<31, 954, (ops GPRC:$rA, GPRC:$rS),
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def EXTSH : XForm_11<31, 922, (ops GPRC:$rA, GPRC:$rS),
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"extsh $rA, $rS", IntGeneral,
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[(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>;
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def EXTSW : XForm_11<31, 986, (ops GPRC:$rA, GPRC:$rS),
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"extsw $rA, $rS", IntRotateD,
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[]>, isPPC64;
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def EXTSW : XForm_11<31, 986, (ops G8RC:$rA, G8RC:$rS),
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"extsw $rA, $rS", IntGeneral,
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[(set G8RC:$rA, (sext_inreg G8RC:$rS, i32))]>, isPPC64;
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def CMP : XForm_16<31, 0, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
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"cmp $crD, $long, $rA, $rB", IntCompare>;
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def CMPL : XForm_16<31, 32, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
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@ -794,7 +794,6 @@ def VXOR : VXForm_1<1220, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vxor $vD, $vA, $vB", VecGeneral,
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[]>;
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//===----------------------------------------------------------------------===//
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// PowerPC Instruction Patterns
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//
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@ -101,7 +101,7 @@ def F26 : FPR<26, "f26">; def F27 : FPR<27, "f27">;
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def F28 : FPR<28, "f28">; def F29 : FPR<29, "f29">;
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def F30 : FPR<30, "f30">; def F31 : FPR<31, "f31">;
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// Floating-point registers
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// Vector registers
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def V0 : VR< 0, "v0">; def V1 : VR< 1, "v1">;
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def V2 : VR< 2, "v2">; def V3 : VR< 3, "v3">;
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def V4 : VR< 4, "v4">; def V5 : VR< 5, "v5">;
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