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Provide a 64 bit variant of mmx.maskmovq intrinsic lowering.
Is there way to avoid explicit target check? git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55238 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -255,6 +255,7 @@ class RPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
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//
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// MMXI - MMX instructions with TB prefix.
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// MMXI64 - MMX instructions with TB prefix valid only in 64 bit mode.
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// MMX2I - MMX / SSE2 instructions with TB and OpSize prefixes.
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// MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
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// MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
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@ -262,6 +263,8 @@ class RPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
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// MMXIS - MMX instructions with XS prefix.
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class MMXI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
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: I<o, F, outs, ins, asm, pattern>, TB, Requires<[HasMMX]>;
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class MMXI64<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
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: I<o, F, outs, ins, asm, pattern>, TB, Requires<[HasMMX,In64BitMode]>;
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class MMXRI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
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: I<o, F, outs, ins, asm, pattern>, TB, REX_W, Requires<[HasMMX]>;
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class MMX2I<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
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@ -491,6 +491,10 @@ let Uses = [EDI] in
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def MMX_MASKMOVQ : MMXI<0xF7, MRMDestMem, (outs), (ins VR64:$src, VR64:$mask),
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"maskmovq\t{$mask, $src|$src, $mask}",
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[(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, EDI)]>;
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let Uses = [RDI] in
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def MMX_MASKMOVQ64: MMXI64<0xF7, MRMDestMem, (outs), (ins VR64:$src, VR64:$mask),
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"maskmovq\t{$mask, $src|$src, $mask}",
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[(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, RDI)]>;
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//===----------------------------------------------------------------------===//
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// Alias Instructions
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