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synced 2024-08-22 10:29:35 +00:00
Remove more filters from the disassembler. Mark some AVX512 instructions as CodeGenOnly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192525 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1177,6 +1177,7 @@ def VMOV64toPQIZrr : AVX512SI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$sr
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[(set VR128X:$dst,
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(v2i64 (scalar_to_vector GR64:$src)))],
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IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
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let isCodeGenOnly = 1 in {
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def VMOV64toSDZrr : AVX512SI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
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"vmovq{z}\t{$src, $dst|$dst, $src}",
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[(set FR64:$dst, (bitconvert GR64:$src))],
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@ -1185,6 +1186,7 @@ def VMOVSDto64Zrr : AVX512SI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src)
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"vmovq{z}\t{$src, $dst|$dst, $src}",
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[(set GR64:$dst, (bitconvert FR64:$src))],
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IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
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}
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def VMOVSDto64Zmr : AVX512SI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
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"vmovq{z}\t{$src, $dst|$dst, $src}",
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[(store (i64 (bitconvert FR64:$src)), addr:$dst)],
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@ -1193,6 +1195,7 @@ def VMOVSDto64Zmr : AVX512SI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$s
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// Move Int Doubleword to Single Scalar
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//
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let isCodeGenOnly = 1 in {
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def VMOVDI2SSZrr : AVX512SI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
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"vmovd{z}\t{$src, $dst|$dst, $src}",
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[(set FR32X:$dst, (bitconvert GR32:$src))],
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@ -1202,6 +1205,7 @@ def VMOVDI2SSZrm : AVX512SI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$sr
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"vmovd{z}\t{$src, $dst|$dst, $src}",
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[(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
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IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
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}
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// Move Packed Doubleword Int to Packed Double Int
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//
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@ -1236,6 +1240,7 @@ def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
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// Move Scalar Single to Double Int
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//
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let isCodeGenOnly = 1 in {
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def VMOVSS2DIZrr : AVX512SI<0x7E, MRMDestReg, (outs GR32:$dst),
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(ins FR32X:$src),
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"vmovd{z}\t{$src, $dst|$dst, $src}",
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@ -1246,6 +1251,7 @@ def VMOVSS2DIZmr : AVX512SI<0x7E, MRMDestMem, (outs),
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"vmovd{z}\t{$src, $dst|$dst, $src}",
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[(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
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IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
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}
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// Move Quadword Int to Packed Quadword Int
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//
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@ -541,11 +541,6 @@ RecognizableInstr::filter_ret RecognizableInstr::filter() const {
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Name == "XRELEASE_PREFIX")
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return FILTER_WEAK;
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if (HasFROperands && Name.find("MOV") != Name.npos &&
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((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
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(Name.find("to") != Name.npos)))
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return FILTER_STRONG;
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return FILTER_NORMAL;
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}
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