From 01aabdac44af241a9a70c3d6ef8d5007e3e80ce1 Mon Sep 17 00:00:00 2001
From: Bill Wendling <isanbard@gmail.com>
Date: Wed, 20 Oct 2010 23:37:40 +0000
Subject: [PATCH] Add encoding for moving a value between two ARM core
 registers and a doublework extension register.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116970 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/ARM/ARMInstrVFP.td     | 34 +++++++++++++++++++++++++------
 test/MC/ARM/simple-fp-encoding.ll |  8 ++++++++
 2 files changed, 36 insertions(+), 6 deletions(-)

diff --git a/lib/Target/ARM/ARMInstrVFP.td b/lib/Target/ARM/ARMInstrVFP.td
index 0b9da8a26ef..a404c977030 100644
--- a/lib/Target/ARM/ARMInstrVFP.td
+++ b/lib/Target/ARM/ARMInstrVFP.td
@@ -505,9 +505,20 @@ def VMOVSR : AVConv4I<0b11100000, 0b1010,
 
 let neverHasSideEffects = 1 in {
 def VMOVRRD  : AVConv3I<0b11000101, 0b1011,
-                      (outs GPR:$wb, GPR:$dst2), (ins DPR:$src),
-                 IIC_fpMOVDI, "vmov", "\t$wb, $dst2, $src",
+                        (outs GPR:$Rt, GPR:$Rt2), (ins DPR:$Dm),
+                        IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $Dm",
                  [/* FIXME: Can't write pattern for multiple result instr*/]> {
+  // Instruction operands.
+  bits<5> Dm;
+  bits<4> Rt;
+  bits<4> Rt2;
+
+  // Encode instruction operands.
+  let Inst{3-0}   = Dm{3-0};
+  let Inst{5}     = Dm{4};
+  let Inst{15-12} = Rt;
+  let Inst{19-16} = Rt2;
+
   let Inst{7-6} = 0b00;
 }
 
@@ -523,10 +534,21 @@ def VMOVRRS  : AVConv3I<0b11000101, 0b1010,
 // FMDLR: GPR -> SPR
 
 def VMOVDRR : AVConv5I<0b11000100, 0b1011,
-                     (outs DPR:$dst), (ins GPR:$src1, GPR:$src2),
-                IIC_fpMOVID, "vmov", "\t$dst, $src1, $src2",
-                [(set DPR:$dst, (arm_fmdrr GPR:$src1, GPR:$src2))]> {
-  let Inst{7-6} = 0b00;
+                      (outs DPR:$Dm), (ins GPR:$Rt, GPR:$Rt2),
+                      IIC_fpMOVID, "vmov", "\t$Dm, $Rt, $Rt2",
+                      [(set DPR:$Dm, (arm_fmdrr GPR:$Rt, GPR:$Rt2))]> {
+  // Instruction operands.
+  bits<5> Dm;
+  bits<4> Rt;
+  bits<4> Rt2;
+
+  // Encode instruction operands.
+  let Inst{3-0}   = Dm{3-0};
+  let Inst{5}     = Dm{4};
+  let Inst{15-12} = Rt;
+  let Inst{19-16} = Rt2;
+
+  let Inst{7-6}   = 0b00;
 }
 
 let neverHasSideEffects = 1 in
diff --git a/test/MC/ARM/simple-fp-encoding.ll b/test/MC/ARM/simple-fp-encoding.ll
index e9ece3529cf..230fc87df75 100644
--- a/test/MC/ARM/simple-fp-encoding.ll
+++ b/test/MC/ARM/simple-fp-encoding.ll
@@ -423,3 +423,11 @@ entry:
 }
 
 declare void @g104(i32, i32, i32, i32, i32, i32)
+
+define double @f105(i32 %a) nounwind readnone {
+entry:
+; CHECK: f105
+; CHECK: vmov r0, r1, d16            @ encoding: [0x30,0x0b,0x51,0xec]
+  %conv = uitofp i32 %a to double
+  ret double %conv
+}