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ARM: provide diagnostics on more writeback LDM/STM instructions

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The set of circumstances where the writeback register is allowed to be in the
list of registers is rather baroque, but I think this implements them all on
the assembly parsing side.

For disassembly, we still warn about an ARM-mode LDM even if the architecture
revision is < v7 (the required architecture information isn't available). It's
a silly instruction anyway, so hopefully no-one will mind.

rdar://problem/15223374

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193185 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover
2013-10-22 19:00:39 +00:00
parent e18273b7be
commit 01b0e94bb7
5 changed files with 80 additions and 17 deletions
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30
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
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@ -1203,20 +1203,22 @@ static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
DecodeStatus S = MCDisassembler::Success;
bool writebackLoad = false;
unsigned writebackReg = 0;
bool NeedDisjointWriteback = false;
unsigned WritebackReg = 0;
switch (Inst.getOpcode()) {
default:
break;
case ARM::LDMIA_UPD:
case ARM::LDMDB_UPD:
case ARM::LDMIB_UPD:
case ARM::LDMDA_UPD:
case ARM::t2LDMIA_UPD:
case ARM::t2LDMDB_UPD:
writebackLoad = true;
writebackReg = Inst.getOperand(0).getReg();
break;
default:
break;
case ARM::LDMIA_UPD:
case ARM::LDMDB_UPD:
case ARM::LDMIB_UPD:
case ARM::LDMDA_UPD:
case ARM::t2LDMIA_UPD:
case ARM::t2LDMDB_UPD:
case ARM::t2STMIA_UPD:
case ARM::t2STMDB_UPD:
NeedDisjointWriteback = true;
WritebackReg = Inst.getOperand(0).getReg();
break;
}
// Empty register lists are not allowed.
@ -1226,7 +1228,7 @@ static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
return MCDisassembler::Fail;
// Writeback not allowed if Rn is in the target list.
if (writebackLoad && writebackReg == Inst.end()[-1].getReg())
if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg())
Check(S, MCDisassembler::SoftFail);
}
}