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AArch64: add support for llvm.aarch64.hint intrinsic

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This adds a llvm.aarch64.hint intrinsic to mirror the llvm.arm.hint in order to
support the various hint intrinsic functions in the ACLE.

Add an optional pattern field that permits the subclass to specify the pattern
that matches the selection.  The intrinsic pattern is set as mayLoad, mayStore,
so overload the value for the definition of the hint instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212883 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Saleem Abdulrasool 2014-07-12 21:20:49 +00:00
parent 1bbed94228
commit 01c06d7954
3 changed files with 89 additions and 11 deletions
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5
include/llvm/IR/IntrinsicsAArch64.td
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@ -32,6 +32,11 @@ def int_aarch64_sdiv : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,
def int_aarch64_udiv : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,
LLVMMatchType<0>], [IntrNoMem]>;
//===----------------------------------------------------------------------===//
// HINT
def int_aarch64_hint : Intrinsic<[], [llvm_i32_ty]>;
//===----------------------------------------------------------------------===//
// RBIT

28
lib/Target/AArch64/AArch64InstrFormats.td
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@ -776,15 +776,17 @@ def simdimmtype10 : Operand<i32>,
// Base encoding for system instruction operands.
let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
class BaseSystemI<bit L, dag oops, dag iops, string asm, string operands>
: I<oops, iops, asm, operands, "", []> {
class BaseSystemI<bit L, dag oops, dag iops, string asm, string operands,
list<dag> pattern = []>
: I<oops, iops, asm, operands, "", pattern> {
let Inst{31-22} = 0b1101010100;
let Inst{21} = L;
}
// System instructions which do not have an Rt register.
class SimpleSystemI<bit L, dag iops, string asm, string operands>
: BaseSystemI<L, (outs), iops, asm, operands> {
class SimpleSystemI<bit L, dag iops, string asm, string operands,
list<dag> pattern = []>
: BaseSystemI<L, (outs), iops, asm, operands, pattern> {
let Inst{4-0} = 0b11111;
}
@ -797,13 +799,17 @@ class RtSystemI<bit L, dag oops, dag iops, string asm, string operands>
}
// Hint instructions that take both a CRm and a 3-bit immediate.
class HintI<string mnemonic>
: SimpleSystemI<0, (ins imm0_127:$imm), mnemonic#" $imm", "">,
Sched<[WriteHint]> {
bits <7> imm;
let Inst{20-12} = 0b000110010;
let Inst{11-5} = imm;
}
// NOTE: ideally, this would have mayStore = 0, mayLoad = 0, but we cannot
// model patterns with sufficiently fine granularity
let mayStore = 1, mayLoad = 1, hasSideEffects = 1 in
class HintI<string mnemonic>
: SimpleSystemI<0, (ins imm0_127:$imm), mnemonic#" $imm", "",
[(int_aarch64_hint imm0_127:$imm)]>,
Sched<[WriteHint]> {
bits <7> imm;
let Inst{20-12} = 0b000110010;
let Inst{11-5} = imm;
}
// System instructions taking a single literal operand which encodes into
// CRm. op2 differentiates the opcodes.

67
test/CodeGen/AArch64/hints.ll Normal file
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@ -0,0 +1,67 @@
; RUN: llc -mtriple aarch64-eabi -o - %s | FileCheck %s
declare void @llvm.aarch64.hint(i32) nounwind
define void @hint_nop() {
entry:
tail call void @llvm.aarch64.hint(i32 0) nounwind
ret void
}
; CHECK-LABEL: hint_nop
; CHECK: nop
define void @hint_yield() {
entry:
tail call void @llvm.aarch64.hint(i32 1) nounwind
ret void
}
; CHECK-LABEL: hint_yield
; CHECK: yield
define void @hint_wfe() {
entry:
tail call void @llvm.aarch64.hint(i32 2) nounwind
ret void
}
; CHECK-LABEL: hint_wfe
; CHECK: wfe
define void @hint_wfi() {
entry:
tail call void @llvm.aarch64.hint(i32 3) nounwind
ret void
}
; CHECK-LABEL: hint_wfi
; CHECK: wfi
define void @hint_sev() {
entry:
tail call void @llvm.aarch64.hint(i32 4) nounwind
ret void
}
; CHECK-LABEL: hint_sev
; CHECK: sev
define void @hint_sevl() {
entry:
tail call void @llvm.aarch64.hint(i32 5) nounwind
ret void
}
; CHECK-LABEL: hint_sevl
; CHECK: sevl
define void @hint_undefined() {
entry:
tail call void @llvm.aarch64.hint(i32 8) nounwind
ret void
}
; CHECK-LABEL: hint_undefined
; CHECK: hint #0x8