mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-08-14 15:28:20 +00:00
Code insertion methods now return void instead of an int.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15780 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
@@ -25,7 +25,7 @@ SparcV8RegisterInfo::SparcV8RegisterInfo()
|
|||||||
: SparcV8GenRegisterInfo(V8::ADJCALLSTACKDOWN,
|
: SparcV8GenRegisterInfo(V8::ADJCALLSTACKDOWN,
|
||||||
V8::ADJCALLSTACKUP) {}
|
V8::ADJCALLSTACKUP) {}
|
||||||
|
|
||||||
int SparcV8RegisterInfo::
|
void SparcV8RegisterInfo::
|
||||||
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
||||||
unsigned SrcReg, int FrameIdx) const {
|
unsigned SrcReg, int FrameIdx) const {
|
||||||
const TargetRegisterClass *RC = getRegClass(SrcReg);
|
const TargetRegisterClass *RC = getRegClass(SrcReg);
|
||||||
@@ -42,10 +42,9 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
|||||||
.addReg (SrcReg);
|
.addReg (SrcReg);
|
||||||
else
|
else
|
||||||
assert (0 && "Can't store this register to stack slot");
|
assert (0 && "Can't store this register to stack slot");
|
||||||
return 1;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
int SparcV8RegisterInfo::
|
void SparcV8RegisterInfo::
|
||||||
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
||||||
unsigned DestReg, int FrameIdx) const {
|
unsigned DestReg, int FrameIdx) const {
|
||||||
const TargetRegisterClass *RC = getRegClass(DestReg);
|
const TargetRegisterClass *RC = getRegClass(DestReg);
|
||||||
@@ -59,10 +58,9 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
|||||||
.addSImm (0);
|
.addSImm (0);
|
||||||
else
|
else
|
||||||
assert(0 && "Can't load this register from stack slot");
|
assert(0 && "Can't load this register from stack slot");
|
||||||
return 1;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
int SparcV8RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
|
void SparcV8RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
|
||||||
MachineBasicBlock::iterator I,
|
MachineBasicBlock::iterator I,
|
||||||
unsigned DestReg, unsigned SrcReg,
|
unsigned DestReg, unsigned SrcReg,
|
||||||
const TargetRegisterClass *RC) const {
|
const TargetRegisterClass *RC) const {
|
||||||
@@ -72,7 +70,6 @@ int SparcV8RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
|
|||||||
BuildMI (MBB, I, V8::FMOVS, 1, DestReg).addReg (SrcReg);
|
BuildMI (MBB, I, V8::FMOVS, 1, DestReg).addReg (SrcReg);
|
||||||
else
|
else
|
||||||
assert (0 && "Can't copy this register");
|
assert (0 && "Can't copy this register");
|
||||||
return 1;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void SparcV8RegisterInfo::
|
void SparcV8RegisterInfo::
|
||||||
|
@@ -26,15 +26,15 @@ struct SparcV8RegisterInfo : public SparcV8GenRegisterInfo {
|
|||||||
const TargetRegisterClass* getRegClassForType(const Type* Ty) const;
|
const TargetRegisterClass* getRegClassForType(const Type* Ty) const;
|
||||||
|
|
||||||
/// Code Generation virtual methods...
|
/// Code Generation virtual methods...
|
||||||
int storeRegToStackSlot(MachineBasicBlock &MBB,
|
void storeRegToStackSlot(MachineBasicBlock &MBB,
|
||||||
MachineBasicBlock::iterator MBBI,
|
MachineBasicBlock::iterator MBBI,
|
||||||
unsigned SrcReg, int FrameIndex) const;
|
unsigned SrcReg, int FrameIndex) const;
|
||||||
|
|
||||||
int loadRegFromStackSlot(MachineBasicBlock &MBB,
|
void loadRegFromStackSlot(MachineBasicBlock &MBB,
|
||||||
MachineBasicBlock::iterator MBBI,
|
MachineBasicBlock::iterator MBBI,
|
||||||
unsigned DestReg, int FrameIndex) const;
|
unsigned DestReg, int FrameIndex) const;
|
||||||
|
|
||||||
int copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
|
void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
|
||||||
unsigned DestReg, unsigned SrcReg,
|
unsigned DestReg, unsigned SrcReg,
|
||||||
const TargetRegisterClass *RC) const;
|
const TargetRegisterClass *RC) const;
|
||||||
|
|
||||||
|
@@ -25,7 +25,7 @@ SparcV8RegisterInfo::SparcV8RegisterInfo()
|
|||||||
: SparcV8GenRegisterInfo(V8::ADJCALLSTACKDOWN,
|
: SparcV8GenRegisterInfo(V8::ADJCALLSTACKDOWN,
|
||||||
V8::ADJCALLSTACKUP) {}
|
V8::ADJCALLSTACKUP) {}
|
||||||
|
|
||||||
int SparcV8RegisterInfo::
|
void SparcV8RegisterInfo::
|
||||||
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
||||||
unsigned SrcReg, int FrameIdx) const {
|
unsigned SrcReg, int FrameIdx) const {
|
||||||
const TargetRegisterClass *RC = getRegClass(SrcReg);
|
const TargetRegisterClass *RC = getRegClass(SrcReg);
|
||||||
@@ -42,10 +42,9 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
|||||||
.addReg (SrcReg);
|
.addReg (SrcReg);
|
||||||
else
|
else
|
||||||
assert (0 && "Can't store this register to stack slot");
|
assert (0 && "Can't store this register to stack slot");
|
||||||
return 1;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
int SparcV8RegisterInfo::
|
void SparcV8RegisterInfo::
|
||||||
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
||||||
unsigned DestReg, int FrameIdx) const {
|
unsigned DestReg, int FrameIdx) const {
|
||||||
const TargetRegisterClass *RC = getRegClass(DestReg);
|
const TargetRegisterClass *RC = getRegClass(DestReg);
|
||||||
@@ -59,10 +58,9 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
|||||||
.addSImm (0);
|
.addSImm (0);
|
||||||
else
|
else
|
||||||
assert(0 && "Can't load this register from stack slot");
|
assert(0 && "Can't load this register from stack slot");
|
||||||
return 1;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
int SparcV8RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
|
void SparcV8RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
|
||||||
MachineBasicBlock::iterator I,
|
MachineBasicBlock::iterator I,
|
||||||
unsigned DestReg, unsigned SrcReg,
|
unsigned DestReg, unsigned SrcReg,
|
||||||
const TargetRegisterClass *RC) const {
|
const TargetRegisterClass *RC) const {
|
||||||
@@ -72,7 +70,6 @@ int SparcV8RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
|
|||||||
BuildMI (MBB, I, V8::FMOVS, 1, DestReg).addReg (SrcReg);
|
BuildMI (MBB, I, V8::FMOVS, 1, DestReg).addReg (SrcReg);
|
||||||
else
|
else
|
||||||
assert (0 && "Can't copy this register");
|
assert (0 && "Can't copy this register");
|
||||||
return 1;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void SparcV8RegisterInfo::
|
void SparcV8RegisterInfo::
|
||||||
|
@@ -26,15 +26,15 @@ struct SparcV8RegisterInfo : public SparcV8GenRegisterInfo {
|
|||||||
const TargetRegisterClass* getRegClassForType(const Type* Ty) const;
|
const TargetRegisterClass* getRegClassForType(const Type* Ty) const;
|
||||||
|
|
||||||
/// Code Generation virtual methods...
|
/// Code Generation virtual methods...
|
||||||
int storeRegToStackSlot(MachineBasicBlock &MBB,
|
void storeRegToStackSlot(MachineBasicBlock &MBB,
|
||||||
MachineBasicBlock::iterator MBBI,
|
MachineBasicBlock::iterator MBBI,
|
||||||
unsigned SrcReg, int FrameIndex) const;
|
unsigned SrcReg, int FrameIndex) const;
|
||||||
|
|
||||||
int loadRegFromStackSlot(MachineBasicBlock &MBB,
|
void loadRegFromStackSlot(MachineBasicBlock &MBB,
|
||||||
MachineBasicBlock::iterator MBBI,
|
MachineBasicBlock::iterator MBBI,
|
||||||
unsigned DestReg, int FrameIndex) const;
|
unsigned DestReg, int FrameIndex) const;
|
||||||
|
|
||||||
int copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
|
void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
|
||||||
unsigned DestReg, unsigned SrcReg,
|
unsigned DestReg, unsigned SrcReg,
|
||||||
const TargetRegisterClass *RC) const;
|
const TargetRegisterClass *RC) const;
|
||||||
|
|
||||||
|
@@ -276,19 +276,19 @@ SparcV9RegisterInfo::SparcV9RegisterInfo ()
|
|||||||
RegisterClasses + 5) {
|
RegisterClasses + 5) {
|
||||||
}
|
}
|
||||||
|
|
||||||
int SparcV9RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
|
void SparcV9RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
|
||||||
MachineBasicBlock::iterator MI,
|
MachineBasicBlock::iterator MI,
|
||||||
unsigned SrcReg, int FrameIndex) const{
|
unsigned SrcReg, int FrameIndex) const{
|
||||||
abort ();
|
abort ();
|
||||||
}
|
}
|
||||||
|
|
||||||
int SparcV9RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
|
void SparcV9RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
|
||||||
MachineBasicBlock::iterator MI,
|
MachineBasicBlock::iterator MI,
|
||||||
unsigned DestReg, int FrameIndex) const {
|
unsigned DestReg, int FrameIndex) const {
|
||||||
abort ();
|
abort ();
|
||||||
}
|
}
|
||||||
|
|
||||||
int SparcV9RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
|
void SparcV9RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
|
||||||
MachineBasicBlock::iterator MI,
|
MachineBasicBlock::iterator MI,
|
||||||
unsigned DestReg, unsigned SrcReg,
|
unsigned DestReg, unsigned SrcReg,
|
||||||
const TargetRegisterClass *RC) const {
|
const TargetRegisterClass *RC) const {
|
||||||
|
@@ -25,13 +25,13 @@ struct SparcV9RegisterInfo : public MRegisterInfo {
|
|||||||
const unsigned *getCalleeSaveRegs() const;
|
const unsigned *getCalleeSaveRegs() const;
|
||||||
|
|
||||||
// The rest of these are stubs... for now.
|
// The rest of these are stubs... for now.
|
||||||
int storeRegToStackSlot (MachineBasicBlock &MBB,
|
void storeRegToStackSlot(MachineBasicBlock &MBB,
|
||||||
MachineBasicBlock::iterator MI,
|
MachineBasicBlock::iterator MI,
|
||||||
unsigned SrcReg, int FrameIndex) const;
|
unsigned SrcReg, int FrameIndex) const;
|
||||||
int loadRegFromStackSlot (MachineBasicBlock &MBB,
|
void loadRegFromStackSlot(MachineBasicBlock &MBB,
|
||||||
MachineBasicBlock::iterator MI,
|
MachineBasicBlock::iterator MI,
|
||||||
unsigned DestReg, int FrameIndex) const;
|
unsigned DestReg, int FrameIndex) const;
|
||||||
int copyRegToReg (MachineBasicBlock &MBB,
|
void copyRegToReg(MachineBasicBlock &MBB,
|
||||||
MachineBasicBlock::iterator MI,
|
MachineBasicBlock::iterator MI,
|
||||||
unsigned DestReg, unsigned SrcReg,
|
unsigned DestReg, unsigned SrcReg,
|
||||||
const TargetRegisterClass *RC) const;
|
const TargetRegisterClass *RC) const;
|
||||||
|
@@ -54,7 +54,7 @@ static unsigned getIdx(const TargetRegisterClass *RC) {
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
int X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
|
void X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
|
||||||
MachineBasicBlock::iterator MI,
|
MachineBasicBlock::iterator MI,
|
||||||
unsigned SrcReg, int FrameIdx) const {
|
unsigned SrcReg, int FrameIdx) const {
|
||||||
static const unsigned Opcode[] =
|
static const unsigned Opcode[] =
|
||||||
@@ -63,10 +63,9 @@ int X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
|
|||||||
MachineInstr *I = addFrameReference(BuildMI(Opcode[getIdx(RC)], 5),
|
MachineInstr *I = addFrameReference(BuildMI(Opcode[getIdx(RC)], 5),
|
||||||
FrameIdx).addReg(SrcReg);
|
FrameIdx).addReg(SrcReg);
|
||||||
MBB.insert(MI, I);
|
MBB.insert(MI, I);
|
||||||
return 1;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
int X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
|
void X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
|
||||||
MachineBasicBlock::iterator MI,
|
MachineBasicBlock::iterator MI,
|
||||||
unsigned DestReg, int FrameIdx)const{
|
unsigned DestReg, int FrameIdx)const{
|
||||||
static const unsigned Opcode[] =
|
static const unsigned Opcode[] =
|
||||||
@@ -74,17 +73,15 @@ int X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
|
|||||||
const TargetRegisterClass *RC = getRegClass(DestReg);
|
const TargetRegisterClass *RC = getRegClass(DestReg);
|
||||||
unsigned OC = Opcode[getIdx(RC)];
|
unsigned OC = Opcode[getIdx(RC)];
|
||||||
MBB.insert(MI, addFrameReference(BuildMI(OC, 4, DestReg), FrameIdx));
|
MBB.insert(MI, addFrameReference(BuildMI(OC, 4, DestReg), FrameIdx));
|
||||||
return 1;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
int X86RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
|
void X86RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
|
||||||
MachineBasicBlock::iterator MI,
|
MachineBasicBlock::iterator MI,
|
||||||
unsigned DestReg, unsigned SrcReg,
|
unsigned DestReg, unsigned SrcReg,
|
||||||
const TargetRegisterClass *RC) const {
|
const TargetRegisterClass *RC) const {
|
||||||
static const unsigned Opcode[] =
|
static const unsigned Opcode[] =
|
||||||
{ X86::MOV8rr, X86::MOV16rr, X86::MOV32rr, X86::FpMOV };
|
{ X86::MOV8rr, X86::MOV16rr, X86::MOV32rr, X86::FpMOV };
|
||||||
MBB.insert(MI, BuildMI(Opcode[getIdx(RC)],1,DestReg).addReg(SrcReg));
|
MBB.insert(MI, BuildMI(Opcode[getIdx(RC)],1,DestReg).addReg(SrcReg));
|
||||||
return 1;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static MachineInstr *MakeMInst(unsigned Opcode, unsigned FrameIndex,
|
static MachineInstr *MakeMInst(unsigned Opcode, unsigned FrameIndex,
|
||||||
|
@@ -27,15 +27,15 @@ struct X86RegisterInfo : public X86GenRegisterInfo {
|
|||||||
const TargetRegisterClass* getRegClassForType(const Type* Ty) const;
|
const TargetRegisterClass* getRegClassForType(const Type* Ty) const;
|
||||||
|
|
||||||
/// Code Generation virtual methods...
|
/// Code Generation virtual methods...
|
||||||
int storeRegToStackSlot(MachineBasicBlock &MBB,
|
void storeRegToStackSlot(MachineBasicBlock &MBB,
|
||||||
MachineBasicBlock::iterator MI,
|
MachineBasicBlock::iterator MI,
|
||||||
unsigned SrcReg, int FrameIndex) const;
|
unsigned SrcReg, int FrameIndex) const;
|
||||||
|
|
||||||
int loadRegFromStackSlot(MachineBasicBlock &MBB,
|
void loadRegFromStackSlot(MachineBasicBlock &MBB,
|
||||||
MachineBasicBlock::iterator MI,
|
MachineBasicBlock::iterator MI,
|
||||||
unsigned DestReg, int FrameIndex) const;
|
unsigned DestReg, int FrameIndex) const;
|
||||||
|
|
||||||
int copyRegToReg(MachineBasicBlock &MBB,
|
void copyRegToReg(MachineBasicBlock &MBB,
|
||||||
MachineBasicBlock::iterator MI,
|
MachineBasicBlock::iterator MI,
|
||||||
unsigned DestReg, unsigned SrcReg,
|
unsigned DestReg, unsigned SrcReg,
|
||||||
const TargetRegisterClass *RC) const;
|
const TargetRegisterClass *RC) const;
|
||||||
|
Reference in New Issue
Block a user