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AMDGPU/SI: Set DwarfRegNum

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This requires a fix in tablegen for the cast<int> from bits<16>
to work in the list initializer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243723 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault
2015-07-31 01:12:10 +00:00
parent 6a224c30a5
commit 01e2215a94
1 changed files with 14 additions and 6 deletions
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20
lib/Target/AMDGPU/SIRegisterInfo.td
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@ -10,10 +10,13 @@
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Declarations that describe the SI registers // Declarations that describe the SI registers
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class SIReg <string n, bits<16> regIdx = 0> : Register<n>,
class SIReg <string n, bits<16> encoding = 0> : Register<n> { DwarfRegNum<[!cast<int>(HWEncoding)]> {
let Namespace = "AMDGPU"; let Namespace = "AMDGPU";
let HWEncoding = encoding;
// This is the not yet the complete register encoding. An additional
// bit is set for VGPRs.
let HWEncoding = regIdx;
} }
// Special Registers // Special Registers
@ -21,7 +24,8 @@ def VCC_LO : SIReg<"vcc_lo", 106>;
def VCC_HI : SIReg<"vcc_hi", 107>; def VCC_HI : SIReg<"vcc_hi", 107>;
// VCC for 64-bit instructions // VCC for 64-bit instructions
def VCC : RegisterWithSubRegs<"vcc", [VCC_LO, VCC_HI]> { def VCC : RegisterWithSubRegs<"vcc", [VCC_LO, VCC_HI]>,
DwarfRegAlias<VCC_LO> {
let Namespace = "AMDGPU"; let Namespace = "AMDGPU";
let SubRegIndices = [sub0, sub1]; let SubRegIndices = [sub0, sub1];
let HWEncoding = 106; let HWEncoding = 106;
@ -30,7 +34,8 @@ def VCC : RegisterWithSubRegs<"vcc", [VCC_LO, VCC_HI]> {
def EXEC_LO : SIReg<"exec_lo", 126>; def EXEC_LO : SIReg<"exec_lo", 126>;
def EXEC_HI : SIReg<"exec_hi", 127>; def EXEC_HI : SIReg<"exec_hi", 127>;
def EXEC : RegisterWithSubRegs<"EXEC", [EXEC_LO, EXEC_HI]> { def EXEC : RegisterWithSubRegs<"EXEC", [EXEC_LO, EXEC_HI]>,
DwarfRegAlias<EXEC_LO> {
let Namespace = "AMDGPU"; let Namespace = "AMDGPU";
let SubRegIndices = [sub0, sub1]; let SubRegIndices = [sub0, sub1];
let HWEncoding = 126; let HWEncoding = 126;
@ -43,7 +48,8 @@ def FLAT_SCR_LO : SIReg<"flat_scr_lo", 104>; // Offset in units of 256-bytes.
def FLAT_SCR_HI : SIReg<"flat_scr_hi", 105>; // Size is the per-thread scratch size, in bytes. def FLAT_SCR_HI : SIReg<"flat_scr_hi", 105>; // Size is the per-thread scratch size, in bytes.
// Pair to indicate location of scratch space for flat accesses. // Pair to indicate location of scratch space for flat accesses.
def FLAT_SCR : RegisterWithSubRegs <"flat_scr", [FLAT_SCR_LO, FLAT_SCR_HI]> { def FLAT_SCR : RegisterWithSubRegs <"flat_scr", [FLAT_SCR_LO, FLAT_SCR_HI]>,
DwarfRegAlias<FLAT_SCR_LO> {
let Namespace = "AMDGPU"; let Namespace = "AMDGPU";
let SubRegIndices = [sub0, sub1]; let SubRegIndices = [sub0, sub1];
let HWEncoding = 104; let HWEncoding = 104;
@ -65,6 +71,8 @@ foreach Index = 0-255 in {
// Groupings using register classes and tuples // Groupings using register classes and tuples
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// TODO: Do we need to set DwarfRegAlias on register tuples?
// SGPR 32-bit registers // SGPR 32-bit registers
def SGPR_32 : RegisterClass<"AMDGPU", [i32, f32], 32, def SGPR_32 : RegisterClass<"AMDGPU", [i32, f32], 32,
(add (sequence "SGPR%u", 0, 101))>; (add (sequence "SGPR%u", 0, 101))>;