diff --git a/lib/Target/PowerPC/PPCFrameLowering.cpp b/lib/Target/PowerPC/PPCFrameLowering.cpp index f6c00f0d32b..6a3951cf613 100644 --- a/lib/Target/PowerPC/PPCFrameLowering.cpp +++ b/lib/Target/PowerPC/PPCFrameLowering.cpp @@ -1094,6 +1094,13 @@ PPCFrameLowering::addScavengingSpillSlot(MachineFunction &MF, RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), RC->getAlignment(), false)); + + // These kinds of spills might need two registers. + if (spillsCR(MF) || spillsVRSAVE(MF)) + RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), + RC->getAlignment(), + false)); + } } diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp index 3d1b83767f0..1fa0f67137c 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -304,14 +304,14 @@ void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II, MachineInstr &MI = *II; // ; SPILL_CR , // Get the instruction's basic block. MachineBasicBlock &MBB = *MI.getParent(); + MachineFunction &MF = *MBB.getParent(); DebugLoc dl = MI.getDebugLoc(); - // FIXME: Once LLVM supports creating virtual registers here, or the register - // scavenger can return multiple registers, stop using reserved registers - // here. - bool LP64 = Subtarget.isPPC64(); - unsigned Reg = LP64 ? PPC::X0 : PPC::R0; + const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; + const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; + + unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); unsigned SrcReg = MI.getOperand(0).getReg(); // We need to store the CR in the low 4-bits of the saved value. First, issue @@ -321,13 +321,17 @@ void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II, // If the saved register wasn't CR0, shift the bits left so that they are in // CR0's slot. - if (SrcReg != PPC::CR0) + if (SrcReg != PPC::CR0) { + unsigned Reg1 = Reg; + Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); + // rlwinm rA, rA, ShiftBits, 0, 31. BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) - .addReg(Reg, RegState::Kill) + .addReg(Reg1, RegState::Kill) .addImm(getPPCRegisterNumbering(SrcReg) * 4) .addImm(0) .addImm(31); + } addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW)) .addReg(Reg, getKillRegState(MI.getOperand(1).getImm())), @@ -343,14 +347,14 @@ void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II, MachineInstr &MI = *II; // ; = RESTORE_CR // Get the instruction's basic block. MachineBasicBlock &MBB = *MI.getParent(); + MachineFunction &MF = *MBB.getParent(); DebugLoc dl = MI.getDebugLoc(); - // FIXME: Once LLVM supports creating virtual registers here, or the register - // scavenger can return multiple registers, stop using reserved registers - // here. - bool LP64 = Subtarget.isPPC64(); - unsigned Reg = LP64 ? PPC::X0 : PPC::R0; + const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; + const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; + + unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); unsigned DestReg = MI.getOperand(0).getReg(); assert(MI.definesRegister(DestReg) && "RESTORE_CR does not define its destination"); @@ -361,15 +365,18 @@ void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II, // If the reloaded register isn't CR0, shift the bits right so that they are // in the right CR's slot. if (DestReg != PPC::CR0) { + unsigned Reg1 = Reg; + Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); + unsigned ShiftBits = getPPCRegisterNumbering(DestReg)*4; // rlwinm r11, r11, 32-ShiftBits, 0, 31. BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) - .addReg(Reg).addImm(32-ShiftBits).addImm(0) + .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0) .addImm(31); } BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTCRF8 : PPC::MTCRF), DestReg) - .addReg(Reg); + .addReg(Reg, RegState::Kill); // Discard the pseudo instruction. MBB.erase(II); @@ -381,13 +388,11 @@ void PPCRegisterInfo::lowerVRSAVESpilling(MachineBasicBlock::iterator II, MachineInstr &MI = *II; // ; SPILL_VRSAVE , // Get the instruction's basic block. MachineBasicBlock &MBB = *MI.getParent(); + MachineFunction &MF = *MBB.getParent(); DebugLoc dl = MI.getDebugLoc(); - // FIXME: Once LLVM supports creating virtual registers here, or the register - // scavenger can return multiple registers, stop using reserved registers - // here. - - unsigned Reg = PPC::R0; + const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; + unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC); unsigned SrcReg = MI.getOperand(0).getReg(); BuildMI(MBB, II, dl, TII.get(PPC::MFVRSAVEv), Reg) @@ -407,13 +412,11 @@ void PPCRegisterInfo::lowerVRSAVERestore(MachineBasicBlock::iterator II, MachineInstr &MI = *II; // ; = RESTORE_VRSAVE // Get the instruction's basic block. MachineBasicBlock &MBB = *MI.getParent(); + MachineFunction &MF = *MBB.getParent(); DebugLoc dl = MI.getDebugLoc(); - // FIXME: Once LLVM supports creating virtual registers here, or the register - // scavenger can return multiple registers, stop using reserved registers - // here. - - unsigned Reg = PPC::R0; + const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; + unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC); unsigned DestReg = MI.getOperand(0).getReg(); assert(MI.definesRegister(DestReg) && "RESTORE_VRSAVE does not define its destination"); @@ -422,7 +425,7 @@ void PPCRegisterInfo::lowerVRSAVERestore(MachineBasicBlock::iterator II, Reg), FrameIndex); BuildMI(MBB, II, dl, TII.get(PPC::MTVRSAVEv), DestReg) - .addReg(Reg); + .addReg(Reg, RegState::Kill); // Discard the pseudo instruction. MBB.erase(II); diff --git a/test/CodeGen/PowerPC/2010-02-12-saveCR.ll b/test/CodeGen/PowerPC/2010-02-12-saveCR.ll index 0da6e4351bd..79e8f96b399 100644 --- a/test/CodeGen/PowerPC/2010-02-12-saveCR.ll +++ b/test/CodeGen/PowerPC/2010-02-12-saveCR.ll @@ -2,21 +2,22 @@ ; ModuleID = 'hh.c' target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128-n32" target triple = "powerpc-apple-darwin9.6" -; This formerly used R0 for both the stack address and CR. define void @foo() nounwind { entry: -;CHECK: mfcr r0 -;CHECK: lis r2, 1 -;CHECK: rlwinm r0, r0, 8, 0, 31 -;CHECK: ori r2, r2, 34540 -;CHECK: stwx r0, r1, r2 -; Make sure that the register scavenger returns the same temporary register. -;CHECK: lis r2, 1 -;CHECK: mfcr r0 -;CHECK: ori r2, r2, 34536 -;CHECK: rlwinm r0, r0, 12, 0, 31 -;CHECK: stwx r0, r1, r2 +; Note that part of what is being checked here is proper register reuse. +; CHECK: mfcr [[T1:r[0-9]+]] ; cr2 +; CHECK: lis [[T2:r[0-9]+]], 1 +; FIXME: There should only be one lis needed here! +; CHECK: lis [[T3:r[0-9]+]], 1 +; CHECK: addi r3, r1, 72 +; CHECK: rlwinm [[T1]], [[T1]], 8, 0, 31 +; CHECK: ori [[T2]], [[T2]], 34540 +; CHECK: ori [[T3]], [[T3]], 34536 +; CHECK: stwx [[T1]], r1, [[T2]] +; CHECK: mfcr [[T4:r[0-9]+]] ; cr3 +; CHECK: rlwinm [[T4]], [[T4]], 12, 0, 31 +; CHECK: stwx r4, r1, [[T3]] %x = alloca [100000 x i8] ; <[100000 x i8]*> [#uses=1] %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] %x1 = bitcast [100000 x i8]* %x to i8* ; [#uses=1] @@ -25,11 +26,16 @@ entry: br label %return return: ; preds = %entry -;CHECK: lis r2, 1 -;CHECK: ori r2, r2, 34540 -;CHECK: lwzx r0, r1, r2 -;CHECK: rlwinm r0, r0, 24, 0, 31 -;CHECK: mtcrf 32, r0 +; CHECK: lis [[T1:r[0-9]+]], 1 +; CHECK: ori [[T1]], [[T1]], 34536 +; CHECK: lwzx [[T1]], r1, [[T1]] +; CHECK: rlwinm [[T1]], [[T1]], 20, 0, 31 +; CHECK: mtcrf 16, [[T1]] +; CHECK: lis [[T1]], 1 +; CHECK: ori [[T1]], [[T1]], 34540 +; CHECK: lwzx [[T1]], r1, [[T1]] +; CHECK: rlwinm [[T1]], [[T1]], 24, 0, 31 +; CHECK: mtcrf 32, [[T1]] ret void }