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[TTI] BasicTTIImpl assumes no vector registers
Summary: Following the discussion on r241884, it's more reasonable to assume that a target has no vector registers by default instead of letting every such target overrides getNumberOfRegisters. Therefore, this patch modifies BasicTTIImpl::getNumberOfRegisters to return 0 when Vector is true, and partially reverts r241884 which modifies NVPTXTTIImpl::getNumberOfRegisters. It also fixes a performance bug in LoopVectorizer. Even if a target has no vector registers, vectorization may still help ILP. So, we need both checks to be false before disabling loop vectorization all together. Reviewers: hfinkel Subscribers: llvm-commits, jholewinski Differential Revision: http://reviews.llvm.org/D11108 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241942 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -276,7 +276,7 @@ public:
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/// \name Vector TTI Implementations
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/// @{
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unsigned getNumberOfRegisters(bool Vector) { return 1; }
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unsigned getNumberOfRegisters(bool Vector) { return Vector ? 0 : 1; }
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unsigned getRegisterBitWidth(bool Vector) { return 32; }
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@ -117,9 +117,3 @@ unsigned NVPTXTTIImpl::getArithmeticInstrCost(
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Opd1PropInfo, Opd2PropInfo);
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}
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}
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unsigned NVPTXTTIImpl::getNumberOfRegisters(bool Vector) {
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if (Vector)
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return 0;
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return BaseT::getNumberOfRegisters(Vector);
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}
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@ -58,8 +58,6 @@ public:
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TTI::OperandValueKind Opd2Info = TTI::OK_AnyValue,
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TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None,
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TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None);
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unsigned getNumberOfRegisters(bool Vector);
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};
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} // end namespace llvm
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@ -1456,9 +1456,14 @@ struct LoopVectorize : public FunctionPass {
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const BranchProbability ColdProb(1, 5); // 20%
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ColdEntryFreq = BlockFrequency(BFI->getEntryFreq()) * ColdProb;
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// If the target claims to have no vector registers don't attempt
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// vectorization.
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if (!TTI->getNumberOfRegisters(true))
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// Don't attempt if
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// 1. the target claims to have no vector registers, and
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// 2. interleaving won't help ILP.
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//
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// The second condition is necessary because, even if the target has no
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// vector registers, loop vectorization may still enable scalar
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// interleaving.
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if (!TTI->getNumberOfRegisters(true) && TTI->getMaxInterleaveFactor(1) < 2)
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return false;
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// Build up a worklist of inner-loops to vectorize. This is necessary as
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