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Fix some shift bugs

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21126 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nate Begeman 2005-04-06 22:42:08 +00:00
parent aeca558788
commit 020ef42c19
1 changed files with 12 additions and 3 deletions
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15
lib/Target/PowerPC/PPC32ISelSimple.cpp
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@ -2779,8 +2779,13 @@ void PPC32ISel::emitShiftOperation(MachineBasicBlock *MBB,
.addImm(32-Amount).addImm(Amount).addImm(31); .addImm(32-Amount).addImm(Amount).addImm(31);
BuildMI(*MBB, IP, PPC::RLWIMI, 5, DestReg+1).addReg(TempReg) BuildMI(*MBB, IP, PPC::RLWIMI, 5, DestReg+1).addReg(TempReg)
.addReg(SrcReg).addImm(32-Amount).addImm(0).addImm(Amount-1); .addReg(SrcReg).addImm(32-Amount).addImm(0).addImm(Amount-1);
BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg) if (isSigned) {
.addImm(32-Amount).addImm(Amount).addImm(31); BuildMI(*MBB, IP, PPC::SRAWI, 2, DestReg).addReg(SrcReg)
.addImm(Amount);
} else {
BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg)
.addImm(32-Amount).addImm(Amount).addImm(31);
}
} }
} else { // Shifting more than 32 bits } else { // Shifting more than 32 bits
Amount -= 32; Amount -= 32;
@ -2805,7 +2810,11 @@ void PPC32ISel::emitShiftOperation(MachineBasicBlock *MBB,
BuildMI(*MBB, IP, PPC::OR, 2, DestReg+1).addReg(SrcReg) BuildMI(*MBB, IP, PPC::OR, 2, DestReg+1).addReg(SrcReg)
.addReg(SrcReg); .addReg(SrcReg);
} }
BuildMI(*MBB, IP,PPC::LI, 1, DestReg).addSImm(0); if (isSigned)
BuildMI(*MBB, IP, PPC::SRAWI, 2, DestReg).addReg(SrcReg)
.addImm(31);
else
BuildMI(*MBB, IP,PPC::LI, 1, DestReg).addSImm(0);
} }
} }
} else { } else {