diff --git a/test/CodeGen/X86/avx-blend.ll b/test/CodeGen/X86/avx-blend.ll index d2a22d70947..327aeff8f8f 100644 --- a/test/CodeGen/X86/avx-blend.ll +++ b/test/CodeGen/X86/avx-blend.ll @@ -2,55 +2,48 @@ ; AVX128 tests: -;CHECK-LABEL: vsel_float: -; select mask is . -; Big endian representation is 0101 = 5. -; '1' means takes the first argument, '0' means takes the second argument. -; This is the opposite of the intel syntax, thus we expect -; the inverted mask: 1010 = 10. -; According to the ABI: -; v1 is in xmm0 => first argument is xmm0. -; v2 is in xmm1 => second argument is xmm1. -; result is in xmm0 => destination argument. -;CHECK: vblendps $10, %xmm1, %xmm0, %xmm0 -;CHECK: ret define <4 x float> @vsel_float(<4 x float> %v1, <4 x float> %v2) { +; CHECK-LABEL: vsel_float: +; CHECK: ## BB#0: +; CHECK-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3] +; CHECK-NEXT: retq %vsel = select <4 x i1> , <4 x float> %v1, <4 x float> %v2 ret <4 x float> %vsel } - -;CHECK-LABEL: vsel_i32: -;CHECK: vblendps $10, %xmm1, %xmm0, %xmm0 -;CHECK: ret define <4 x i32> @vsel_i32(<4 x i32> %v1, <4 x i32> %v2) { +; CHECK-LABEL: vsel_i32: +; CHECK: ## BB#0: +; CHECK-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3] +; CHECK-NEXT: retq %vsel = select <4 x i1> , <4 x i32> %v1, <4 x i32> %v2 ret <4 x i32> %vsel } - -;CHECK-LABEL: vsel_double: -;CHECK: vmovsd -;CHECK: ret define <2 x double> @vsel_double(<2 x double> %v1, <2 x double> %v2) { +; CHECK-LABEL: vsel_double: +; CHECK: ## BB#0: +; CHECK-NEXT: vmovsd %xmm0, %xmm1, %xmm0 +; CHECK-NEXT: retq %vsel = select <2 x i1> , <2 x double> %v1, <2 x double> %v2 ret <2 x double> %vsel } - -;CHECK-LABEL: vsel_i64: -;CHECK: vmovsd -;CHECK: ret define <2 x i64> @vsel_i64(<2 x i64> %v1, <2 x i64> %v2) { +; CHECK-LABEL: vsel_i64: +; CHECK: ## BB#0: +; CHECK-NEXT: vmovsd %xmm0, %xmm1, %xmm0 +; CHECK-NEXT: retq %vsel = select <2 x i1> , <2 x i64> %v1, <2 x i64> %v2 ret <2 x i64> %vsel } - -;CHECK-LABEL: vsel_i8: -;CHECK: vpblendvb -;CHECK: ret define <16 x i8> @vsel_i8(<16 x i8> %v1, <16 x i8> %v2) { +; CHECK-LABEL: vsel_i8: +; CHECK: ## BB#0: +; CHECK-NEXT: vmovdqa {{.*#+}} xmm2 = [255,0,0,0,255,0,0,0,255,0,0,0,255,0,0,0] +; CHECK-NEXT: vpblendvb %xmm2, %xmm0, %xmm1, %xmm0 +; CHECK-NEXT: retq %vsel = select <16 x i1> , <16 x i8> %v1, <16 x i8> %v2 ret <16 x i8> %vsel } @@ -58,79 +51,70 @@ define <16 x i8> @vsel_i8(<16 x i8> %v1, <16 x i8> %v2) { ; AVX256 tests: - -;CHECK-LABEL: vsel_float8: -;CHECK-NOT: vinsertf128 -; -; which translates into the boolean mask (big endian representation): -; 00010001 = 17. -; '1' means takes the first argument, '0' means takes the second argument. -; This is the opposite of the intel syntax, thus we expect -; the inverted mask: 11101110 = 238. -;CHECK: vblendps $238, %ymm1, %ymm0, %ymm0 -;CHECK: ret define <8 x float> @vsel_float8(<8 x float> %v1, <8 x float> %v2) { +; CHECK-LABEL: vsel_float8: +; CHECK: ## BB#0: +; CHECK-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3],ymm0[4],ymm1[5,6,7] +; CHECK-NEXT: retq %vsel = select <8 x i1> , <8 x float> %v1, <8 x float> %v2 ret <8 x float> %vsel } -;CHECK-LABEL: vsel_i328: -;CHECK-NOT: vinsertf128 -;CHECK: vblendps $238, %ymm1, %ymm0, %ymm0 -;CHECK-NEXT: ret define <8 x i32> @vsel_i328(<8 x i32> %v1, <8 x i32> %v2) { +; CHECK-LABEL: vsel_i328: +; CHECK: ## BB#0: +; CHECK-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3],ymm0[4],ymm1[5,6,7] +; CHECK-NEXT: retq %vsel = select <8 x i1> , <8 x i32> %v1, <8 x i32> %v2 ret <8 x i32> %vsel } -;CHECK-LABEL: vsel_double8: -; select mask is 2x: 0001 => intel mask: ~0001 = 14 -; ABI: -; v1 is in ymm0 and ymm1. -; v2 is in ymm2 and ymm3. -; result is in ymm0 and ymm1. -; Compute the low part: res.low = blend v1.low, v2.low, blendmask -;CHECK: vblendpd $14, %ymm2, %ymm0, %ymm0 -; Compute the high part. -;CHECK: vblendpd $14, %ymm3, %ymm1, %ymm1 -;CHECK: ret define <8 x double> @vsel_double8(<8 x double> %v1, <8 x double> %v2) { +; CHECK-LABEL: vsel_double8: +; CHECK: ## BB#0: +; CHECK-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm2[1,2,3] +; CHECK-NEXT: vblendpd {{.*#+}} ymm1 = ymm1[0],ymm3[1,2,3] +; CHECK-NEXT: retq %vsel = select <8 x i1> , <8 x double> %v1, <8 x double> %v2 ret <8 x double> %vsel } -;CHECK-LABEL: vsel_i648: -;CHECK: vblendpd $14, %ymm2, %ymm0, %ymm0 -;CHECK: vblendpd $14, %ymm3, %ymm1, %ymm1 -;CHECK: ret define <8 x i64> @vsel_i648(<8 x i64> %v1, <8 x i64> %v2) { +; CHECK-LABEL: vsel_i648: +; CHECK: ## BB#0: +; CHECK-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm2[1,2,3] +; CHECK-NEXT: vblendpd {{.*#+}} ymm1 = ymm1[0],ymm3[1,2,3] +; CHECK-NEXT: retq %vsel = select <8 x i1> , <8 x i64> %v1, <8 x i64> %v2 ret <8 x i64> %vsel } -;CHECK-LABEL: vsel_double4: -;CHECK-NOT: vinsertf128 -;CHECK: vblendpd $10 -;CHECK-NEXT: ret define <4 x double> @vsel_double4(<4 x double> %v1, <4 x double> %v2) { +; CHECK-LABEL: vsel_double4: +; CHECK: ## BB#0: +; CHECK-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3] +; CHECK-NEXT: retq %vsel = select <4 x i1> , <4 x double> %v1, <4 x double> %v2 ret <4 x double> %vsel } -;; TEST blend + compares -; CHECK: testa define <2 x double> @testa(<2 x double> %x, <2 x double> %y) { - ; CHECK: vcmplepd - ; CHECK: vblendvpd +; CHECK-LABEL: testa: +; CHECK: ## BB#0: +; CHECK-NEXT: vcmplepd %xmm0, %xmm1, %xmm2 +; CHECK-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0 +; CHECK-NEXT: retq %max_is_x = fcmp oge <2 x double> %x, %y %max = select <2 x i1> %max_is_x, <2 x double> %x, <2 x double> %y ret <2 x double> %max } -; CHECK: testb define <2 x double> @testb(<2 x double> %x, <2 x double> %y) { - ; CHECK: vcmpnlepd - ; CHECK: vblendvpd +; CHECK-LABEL: testb: +; CHECK: ## BB#0: +; CHECK-NEXT: vcmpnlepd %xmm0, %xmm1, %xmm2 +; CHECK-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0 +; CHECK-NEXT: retq %min_is_x = fcmp ult <2 x double> %x, %y %min = select <2 x i1> %min_is_x, <2 x double> %x, <2 x double> %y ret <2 x double> %min @@ -140,18 +124,18 @@ define <2 x double> @testb(<2 x double> %x, <2 x double> %y) { ; blend instruction with an immediate mask define <4 x double> @constant_blendvpd_avx(<4 x double> %xy, <4 x double> %ab) { ; CHECK-LABEL: constant_blendvpd_avx: -; CHECK-NOT: mov -; CHECK: vblendpd -; CHECK: ret +; CHECK: ## BB#0: +; CHECK-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2],ymm1[3] +; CHECK-NEXT: retq %1 = select <4 x i1> , <4 x double> %xy, <4 x double> %ab ret <4 x double> %1 } define <8 x float> @constant_blendvps_avx(<8 x float> %xyzw, <8 x float> %abcd) { ; CHECK-LABEL: constant_blendvps_avx: -; CHECK-NOT: mov -; CHECK: vblendps -; CHECK: ret +; CHECK: ## BB#0: +; CHECK-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3],ymm1[4,5,6],ymm0[7] +; CHECK-NEXT: retq %1 = select <8 x i1> , <8 x float> %xyzw, <8 x float> %abcd ret <8 x float> %1 } @@ -160,43 +144,38 @@ declare <8 x float> @llvm.x86.avx.blendv.ps.256(<8 x float>, <8 x float>, <8 x f declare <4 x double> @llvm.x86.avx.blendv.pd.256(<4 x double>, <4 x double>, <4 x double>) ;; 4 tests for shufflevectors that optimize to blend + immediate -; CHECK-LABEL: @blend_shufflevector_4xfloat define <4 x float> @blend_shufflevector_4xfloat(<4 x float> %a, <4 x float> %b) { -; Equivalent select mask is . -; Big endian representation is 0101 = 5. -; '1' means takes the first argument, '0' means takes the second argument. -; This is the opposite of the intel syntax, thus we expect -; Inverted mask: 1010 = 10. -; According to the ABI: -; a is in xmm0 => first argument is xmm0. -; b is in xmm1 => second argument is xmm1. -; Result is in xmm0 => destination argument. -; CHECK: vblendps $10, %xmm1, %xmm0, %xmm0 -; CHECK: ret +; CHECK-LABEL: blend_shufflevector_4xfloat: +; CHECK: ## BB#0: +; CHECK-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3] +; CHECK-NEXT: retq %1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> ret <4 x float> %1 } -; CHECK-LABEL: @blend_shufflevector_8xfloat define <8 x float> @blend_shufflevector_8xfloat(<8 x float> %a, <8 x float> %b) { -; CHECK: vblendps $190, %ymm1, %ymm0, %ymm0 -; CHECK: ret +; CHECK-LABEL: blend_shufflevector_8xfloat: +; CHECK: ## BB#0: +; CHECK-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3,4,5],ymm0[6],ymm1[7] +; CHECK-NEXT: retq %1 = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> ret <8 x float> %1 } -; CHECK-LABEL: @blend_shufflevector_4xdouble define <4 x double> @blend_shufflevector_4xdouble(<4 x double> %a, <4 x double> %b) { -; CHECK: vblendpd $2, %ymm1, %ymm0, %ymm0 -; CHECK: ret +; CHECK-LABEL: blend_shufflevector_4xdouble: +; CHECK: ## BB#0: +; CHECK-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2,3] +; CHECK-NEXT: retq %1 = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> ret <4 x double> %1 } -; CHECK-LABEL: @blend_shufflevector_4xi64 define <4 x i64> @blend_shufflevector_4xi64(<4 x i64> %a, <4 x i64> %b) { -; CHECK: vblendpd $13, %ymm1, %ymm0, %ymm0 -; CHECK: ret +; CHECK-LABEL: blend_shufflevector_4xi64: +; CHECK: ## BB#0: +; CHECK-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2,3] +; CHECK-NEXT: retq %1 = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> ret <4 x i64> %1 }