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https://github.com/c64scene-ar/llvm-6502.git
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Move a bunch of non-deprecated methods above the "deprecated line"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23216 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -175,6 +175,34 @@ public:
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return get(Opcode).Flags & M_TERMINATOR_FLAG;
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return get(Opcode).Flags & M_TERMINATOR_FLAG;
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}
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}
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bool isBranch(MachineOpCode Opcode) const {
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return get(Opcode).Flags & M_BRANCH_FLAG;
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}
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/// isBarrier - Returns true if the specified instruction stops control flow
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/// from executing the instruction immediately following it. Examples include
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/// unconditional branches and return instructions.
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bool isBarrier(MachineOpCode Opcode) const {
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return get(Opcode).Flags & M_BARRIER_FLAG;
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}
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bool isCall(MachineOpCode Opcode) const {
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return get(Opcode).Flags & M_CALL_FLAG;
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}
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bool isLoad(MachineOpCode Opcode) const {
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return get(Opcode).Flags & M_LOAD_FLAG;
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}
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bool isStore(MachineOpCode Opcode) const {
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return get(Opcode).Flags & M_STORE_FLAG;
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}
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/// usesCustomDAGSchedInsertionHook - Return true if this instruction requires
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/// custom insertion support when the DAG scheduler is inserting it into a
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/// machine basic block.
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bool usesCustomDAGSchedInsertionHook(unsigned Opcode) const {
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return get(Opcode).Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION;
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}
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/// Return true if the instruction is a register to register move
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/// Return true if the instruction is a register to register move
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/// and leave the source and dest operands in the passed parameters.
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/// and leave the source and dest operands in the passed parameters.
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virtual bool isMoveInstr(const MachineInstr& MI,
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virtual bool isMoveInstr(const MachineInstr& MI,
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@ -225,6 +253,7 @@ public:
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return MI;
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return MI;
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}
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}
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//-------------------------------------------------------------------------
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//-------------------------------------------------------------------------
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// Code generation support for creating individual machine instructions
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// Code generation support for creating individual machine instructions
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//
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//
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@ -243,25 +272,6 @@ public:
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bool isNop(MachineOpCode Opcode) const {
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bool isNop(MachineOpCode Opcode) const {
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return get(Opcode).Flags & M_NOP_FLAG;
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return get(Opcode).Flags & M_NOP_FLAG;
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}
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}
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bool isBranch(MachineOpCode Opcode) const {
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return get(Opcode).Flags & M_BRANCH_FLAG;
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}
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/// isBarrier - Returns true if the specified instruction stops control flow
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/// from executing the instruction immediately following it. Examples include
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/// unconditional branches and return instructions.
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bool isBarrier(MachineOpCode Opcode) const {
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return get(Opcode).Flags & M_BARRIER_FLAG;
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}
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bool isCall(MachineOpCode Opcode) const {
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return get(Opcode).Flags & M_CALL_FLAG;
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}
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bool isLoad(MachineOpCode Opcode) const {
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return get(Opcode).Flags & M_LOAD_FLAG;
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}
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bool isStore(MachineOpCode Opcode) const {
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return get(Opcode).Flags & M_STORE_FLAG;
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}
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/// hasDelaySlot - Returns true if the specified instruction has a delay slot
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/// hasDelaySlot - Returns true if the specified instruction has a delay slot
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/// which must be filled by the code generator.
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/// which must be filled by the code generator.
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@ -269,13 +279,6 @@ public:
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return get(Opcode).Flags & M_DELAY_SLOT_FLAG;
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return get(Opcode).Flags & M_DELAY_SLOT_FLAG;
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}
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}
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/// usesCustomDAGSchedInsertionHook - Return true if this instruction requires
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/// custom insertion support when the DAG scheduler is inserting it into a
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/// machine basic block.
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bool usesCustomDAGSchedInsertionHook(unsigned Opcode) const {
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return get(Opcode).Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION;
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}
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virtual bool hasResultInterlock(MachineOpCode Opcode) const {
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virtual bool hasResultInterlock(MachineOpCode Opcode) const {
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return true;
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return true;
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}
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}
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