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Move target independent td files from lib/Target/ to include/llvm/Target so they can be distributed along with the header files.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59953 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2008-11-24 07:34:46 +00:00
parent 24ac408ce8
commit 027fdbe3ba
15 changed files with 17 additions and 16 deletions
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7
Makefile.rules
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@ -1259,9 +1259,10 @@ $(ObjDir)/%.bc: %.ll $(ObjDir)/.dir $(LLVMAS)
ifdef TARGET
TDFiles := $(strip $(wildcard $(PROJ_SRC_DIR)/*.td) \
$(LLVM_SRC_ROOT)/lib/Target/Target.td \
$(LLVM_SRC_ROOT)/lib/Target/TargetCallingConv.td \
$(LLVM_SRC_ROOT)/lib/Target/TargetSelectionDAG.td \
$(LLVM_SRC_ROOT)/include/llvm/Target/Target.td \
$(LLVM_SRC_ROOT)/include/llvm/Target/TargetCallingConv.td \
$(LLVM_SRC_ROOT)/include/llvm/Target/TargetSchedule.td \
$(LLVM_SRC_ROOT)/include/llvm/Target/TargetSelectionDAG.td \
$(LLVM_SRC_ROOT)/include/llvm/CodeGen/ValueTypes.td) \
$(wildcard $(LLVM_SRC_ROOT)/include/llvm/Intrinsics*.td)
INCFiles := $(filter %.inc,$(BUILT_SOURCES))

6
lib/Target/Target.td → include/llvm/Target/Target.td
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@ -147,7 +147,7 @@ class DwarfRegNum<list<int> Numbers> {
//===----------------------------------------------------------------------===//
// Pull in the common support for scheduling
//
include "TargetSchedule.td"
include "llvm/Target/TargetSchedule.td"
class Predicate; // Forward def
@ -491,9 +491,9 @@ class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> {
//===----------------------------------------------------------------------===//
// Pull in the common support for calling conventions.
//
include "TargetCallingConv.td"
include "llvm/Target/TargetCallingConv.td"
//===----------------------------------------------------------------------===//
// Pull in the common support for DAG isel generation.
//
include "TargetSelectionDAG.td"
include "llvm/Target/TargetSelectionDAG.td"

0
lib/Target/TargetCallingConv.td → include/llvm/Target/TargetCallingConv.td
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0
lib/Target/TargetSchedule.td → include/llvm/Target/TargetSchedule.td
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0
lib/Target/TargetSelectionDAG.td → include/llvm/Target/TargetSelectionDAG.td
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2
lib/Target/ARM/ARM.td
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@ -14,7 +14,7 @@
// Target-independent interfaces which we are implementing
//===----------------------------------------------------------------------===//
include "../Target.td"
include "llvm/Target/Target.td"
//===----------------------------------------------------------------------===//
// ARM Subtarget features.

2
lib/Target/Alpha/Alpha.td
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@ -12,7 +12,7 @@
// Get the target-independent interfaces which we are implementing...
//
include "../Target.td"
include "llvm/Target/Target.td"
//Alpha is little endian

2
lib/Target/CellSPU/SPU.td
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@ -13,7 +13,7 @@
// Get the target-independent interfaces which we are implementing.
//
include "../Target.td"
include "llvm/Target/Target.td"
//===----------------------------------------------------------------------===//
// Register File Description

2
lib/Target/IA64/IA64.td
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@ -14,7 +14,7 @@
// Get the target-independent interfaces which we are implementing...
//
include "../Target.td"
include "llvm/Target/Target.td"
//===----------------------------------------------------------------------===//
// Register File Description

2
lib/Target/Mips/Mips.td
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@ -13,7 +13,7 @@
// Target-independent interfaces
//===----------------------------------------------------------------------===//
include "../Target.td"
include "llvm/Target/Target.td"
//===----------------------------------------------------------------------===//
// Register File, Calling Conv, Instruction Descriptions

2
lib/Target/PIC16/PIC16.td
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@ -13,7 +13,7 @@
// Target-independent interfaces
//===----------------------------------------------------------------------===//
include "../Target.td"
include "llvm/Target/Target.td"
include "PIC16RegisterInfo.td"
include "PIC16InstrInfo.td"

2
lib/Target/PowerPC/PPC.td
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@ -13,7 +13,7 @@
// Get the target-independent interfaces which we are implementing.
//
include "../Target.td"
include "llvm/Target/Target.td"
//===----------------------------------------------------------------------===//
// PowerPC Subtarget features.

2
lib/Target/Sparc/Sparc.td
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@ -14,7 +14,7 @@
// Target-independent interfaces which we are implementing
//===----------------------------------------------------------------------===//
include "../Target.td"
include "llvm/Target/Target.td"
//===----------------------------------------------------------------------===//
// SPARC Subtarget features.

2
lib/Target/X86/X86.td
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@ -14,7 +14,7 @@
// Get the target-independent interfaces which we are implementing...
//
include "../Target.td"
include "llvm/Target/Target.td"
//===----------------------------------------------------------------------===//
// X86 Subtarget features.

2
lib/Target/XCore/XCore.td
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@ -14,7 +14,7 @@
// Target-independent interfaces which we are implementing
//===----------------------------------------------------------------------===//
include "../Target.td"
include "llvm/Target/Target.td"
//===----------------------------------------------------------------------===//
// Descriptions