diff --git a/lib/Target/AArch64/AArch64InstrNEON.td b/lib/Target/AArch64/AArch64InstrNEON.td index c0c572a62e7..af7aea6f9d3 100644 --- a/lib/Target/AArch64/AArch64InstrNEON.td +++ b/lib/Target/AArch64/AArch64InstrNEON.td @@ -1592,29 +1592,29 @@ def Neon_High4S : PatFrag<(ops node:$in), (extract_subvector (v4i32 node:$in), (iPTR 2))>; def Neon_High2D : PatFrag<(ops node:$in), (extract_subvector (v2i64 node:$in), (iPTR 1))>; -def Neon_High4f : PatFrag<(ops node:$in), - (extract_subvector (v4f32 node:$in), (iPTR 2))>; -def Neon_High2d : PatFrag<(ops node:$in), - (extract_subvector (v2f64 node:$in), (iPTR 1))>; +def Neon_High4float : PatFrag<(ops node:$in), + (extract_subvector (v4f32 node:$in), (iPTR 2))>; +def Neon_High2double : PatFrag<(ops node:$in), + (extract_subvector (v2f64 node:$in), (iPTR 1))>; -def Neon_low16B : PatFrag<(ops node:$in), +def Neon_Low16B : PatFrag<(ops node:$in), (v8i8 (extract_subvector (v16i8 node:$in), (iPTR 0)))>; -def Neon_low8H : PatFrag<(ops node:$in), +def Neon_Low8H : PatFrag<(ops node:$in), (v4i16 (extract_subvector (v8i16 node:$in), (iPTR 0)))>; -def Neon_low4S : PatFrag<(ops node:$in), +def Neon_Low4S : PatFrag<(ops node:$in), (v2i32 (extract_subvector (v4i32 node:$in), (iPTR 0)))>; -def Neon_low2D : PatFrag<(ops node:$in), +def Neon_Low2D : PatFrag<(ops node:$in), (v1i64 (extract_subvector (v2i64 node:$in), (iPTR 0)))>; -def Neon_low4f : PatFrag<(ops node:$in), - (v2f32 (extract_subvector (v4f32 node:$in), - (iPTR 0)))>; -def Neon_low2d : PatFrag<(ops node:$in), - (v1f64 (extract_subvector (v2f64 node:$in), - (iPTR 0)))>; +def Neon_Low4float : PatFrag<(ops node:$in), + (v2f32 (extract_subvector (v4f32 node:$in), + (iPTR 0)))>; +def Neon_Low2double : PatFrag<(ops node:$in), + (v1f64 (extract_subvector (v2f64 node:$in), + (iPTR 0)))>; def neon_uimm3_shift : Operand, ImmLeaf { @@ -5871,17 +5871,17 @@ multiclass NeonI_Scalar_DUP_Elt_pattern { def : Pat<(ResTy (GetLow VPR128:$Rn)), - (ResTy (DUPdv_D (OpTy VPR128:$Rn), 0))>; + (ResTy (EXTRACT_SUBREG (OpTy VPR128:$Rn), sub_64))>; def : Pat<(ResTy (GetHigh VPR128:$Rn)), (ResTy (DUPdv_D (OpTy VPR128:$Rn), 1))>; } -defm : NeonI_SDUP; -defm : NeonI_SDUP; -defm : NeonI_SDUP; -defm : NeonI_SDUP; -defm : NeonI_SDUP; -defm : NeonI_SDUP; +defm : NeonI_SDUP; +defm : NeonI_SDUP; +defm : NeonI_SDUP; +defm : NeonI_SDUP; +defm : NeonI_SDUP; +defm : NeonI_SDUP; // Patterns for vector extract of FP data using scalar DUP instructions defm : NeonI_Scalar_DUP_Elt_pattern def : NI_2VE_laneq(subop # "_2s4s"), neon_uimm2_bare, op, VPR64, VPR64, VPR128, v2i32, v2i32, v4i32, BinOpFrag<(Neon_vduplane - (Neon_low4S node:$LHS), node:$RHS)>>; + (Neon_Low4S node:$LHS), node:$RHS)>>; def : NI_2VE_laneq(subop # "_4s4s"), neon_uimm2_bare, op, VPR128, VPR128, VPR128, v4i32, v4i32, v4i32, @@ -6241,7 +6241,7 @@ multiclass NI_2VE_v1_pat def : NI_2VE_laneq(subop # "_4h8h"), neon_uimm3_bare, op, VPR64, VPR64, VPR128Lo, v4i16, v4i16, v8i16, BinOpFrag<(Neon_vduplane - (Neon_low8H node:$LHS), node:$RHS)>>; + (Neon_Low8H node:$LHS), node:$RHS)>>; def : NI_2VE_laneq(subop # "_8h8h"), neon_uimm3_bare, op, VPR128, VPR128, VPR128Lo, v8i16, v8i16, v8i16, @@ -6349,7 +6349,7 @@ multiclass NI_2VE_mul_v1_pat { def : NI_2VE_mul_laneq(subop # "_2s4s"), neon_uimm2_bare, op, VPR64, VPR128, v2i32, v2i32, v4i32, BinOpFrag<(Neon_vduplane - (Neon_low4S node:$LHS), node:$RHS)>>; + (Neon_Low4S node:$LHS), node:$RHS)>>; def : NI_2VE_mul_laneq(subop # "_4s4s"), neon_uimm2_bare, op, VPR128, VPR128, v4i32, v4i32, v4i32, @@ -6358,7 +6358,7 @@ multiclass NI_2VE_mul_v1_pat { def : NI_2VE_mul_laneq(subop # "_4h8h"), neon_uimm3_bare, op, VPR64, VPR128Lo, v4i16, v4i16, v8i16, BinOpFrag<(Neon_vduplane - (Neon_low8H node:$LHS), node:$RHS)>>; + (Neon_Low8H node:$LHS), node:$RHS)>>; def : NI_2VE_mul_laneq(subop # "_8h8h"), neon_uimm3_bare, op, VPR128, VPR128Lo, v8i16, v8i16, v8i16, @@ -6435,7 +6435,7 @@ multiclass NI_2VE_mul_v2_pat { def : NI_2VE_mul_laneq(subop # "_2s4s"), neon_uimm2_bare, op, VPR64, VPR128, v2f32, v2f32, v4f32, BinOpFrag<(Neon_vduplane - (Neon_low4f node:$LHS), node:$RHS)>>; + (Neon_Low4float node:$LHS), node:$RHS)>>; def : NI_2VE_mul_laneq(subop # "_4s4s"), neon_uimm2_bare, op, VPR128, VPR128, v4f32, v4f32, v4f32, @@ -6532,7 +6532,7 @@ multiclass NI_2VE_fma_v2_pat { def : NI_2VEswap_laneq(subop # "_2s4s"), neon_uimm2_bare, op, VPR64, VPR128, v2f32, v4f32, BinOpFrag<(Neon_vduplane - (Neon_low4f node:$LHS), node:$RHS)>>; + (Neon_Low4float node:$LHS), node:$RHS)>>; def : NI_2VEswap_laneq(subop # "_4s4s"), neon_uimm2_bare, op, VPR128, VPR128, v4f32, v4f32, @@ -6566,12 +6566,12 @@ multiclass NI_2VE_fms_v2_pat def : NI_2VEswap_laneq(subop # "_2s4s"), neon_uimm2_bare, op, VPR64, VPR128, v2f32, v4f32, BinOpFrag<(fneg (Neon_vduplane - (Neon_low4f node:$LHS), node:$RHS))>>; + (Neon_Low4float node:$LHS), node:$RHS))>>; def : NI_2VEswap_laneq(subop # "_2s4s"), neon_uimm2_bare, op, VPR64, VPR128, v2f32, v4f32, BinOpFrag<(Neon_vduplane - (Neon_low4f (fneg node:$LHS)), + (Neon_Low4float (fneg node:$LHS)), node:$RHS)>>; def : NI_2VEswap_laneq(subop # "_4s4s"), @@ -6739,22 +6739,22 @@ multiclass NI_2VEL_v3_pat { def : NI_2VE_laneq(subop # "_4s4h"), neon_uimm3_bare, op, VPR128, VPR64, VPR128Lo, v4i32, v4i16, v8i16, BinOpFrag<(Neon_vduplane - (Neon_low8H node:$LHS), node:$RHS)>>; + (Neon_Low8H node:$LHS), node:$RHS)>>; def : NI_2VE_laneq(subop # "_2d2s"), neon_uimm2_bare, op, VPR128, VPR64, VPR128, v2i64, v2i32, v4i32, BinOpFrag<(Neon_vduplane - (Neon_low4S node:$LHS), node:$RHS)>>; + (Neon_Low4S node:$LHS), node:$RHS)>>; def : NI_2VEL2_laneq(subop # "_4s8h"), neon_uimm3_bare, op, VPR128Lo, v4i32, v8i16, v8i16, v4i16, Neon_High8H, BinOpFrag<(Neon_vduplane - (Neon_low8H node:$LHS), node:$RHS)>>; + (Neon_Low8H node:$LHS), node:$RHS)>>; def : NI_2VEL2_laneq(subop # "_2d4s"), neon_uimm2_bare, op, VPR128, v2i64, v4i32, v4i32, v2i32, Neon_High4S, BinOpFrag<(Neon_vduplane - (Neon_low4S node:$LHS), node:$RHS)>>; + (Neon_Low4S node:$LHS), node:$RHS)>>; // Index can only be half of the max value for lane in 64-bit vector @@ -6805,23 +6805,23 @@ multiclass NI_2VEL_mul_v3_pat { def : NI_2VE_mul_laneq(subop # "_4s4h"), neon_uimm3_bare, op, VPR64, VPR128Lo, v4i32, v4i16, v8i16, BinOpFrag<(Neon_vduplane - (Neon_low8H node:$LHS), node:$RHS)>>; + (Neon_Low8H node:$LHS), node:$RHS)>>; def : NI_2VE_mul_laneq(subop # "_2d2s"), neon_uimm2_bare, op, VPR64, VPR128, v2i64, v2i32, v4i32, BinOpFrag<(Neon_vduplane - (Neon_low4S node:$LHS), node:$RHS)>>; + (Neon_Low4S node:$LHS), node:$RHS)>>; def : NI_2VEL2_mul_laneq(subop # "_4s8h"), neon_uimm3_bare, op, VPR128Lo, v4i32, v8i16, v8i16, v4i16, Neon_High8H, BinOpFrag<(Neon_vduplane - (Neon_low8H node:$LHS), node:$RHS)>>; + (Neon_Low8H node:$LHS), node:$RHS)>>; def : NI_2VEL2_mul_laneq(subop # "_2d4s"), neon_uimm2_bare, op, VPR128, v2i64, v4i32, v4i32, v2i32, Neon_High4S, BinOpFrag<(Neon_vduplane - (Neon_low4S node:$LHS), node:$RHS)>>; + (Neon_Low4S node:$LHS), node:$RHS)>>; // Index can only be half of the max value for lane in 64-bit vector @@ -6864,25 +6864,25 @@ multiclass NI_2VEL_v3_qdma_pat { !cast(op # "_4s"), VPR128, VPR64, VPR128Lo, v4i32, v4i16, v8i16, BinOpFrag<(Neon_vduplane - (Neon_low8H node:$LHS), node:$RHS)>>; + (Neon_Low8H node:$LHS), node:$RHS)>>; def : NI_2VE_laneq(subop # "_2d2s"), neon_uimm2_bare, !cast(op # "_2d"), VPR128, VPR64, VPR128, v2i64, v2i32, v4i32, BinOpFrag<(Neon_vduplane - (Neon_low4S node:$LHS), node:$RHS)>>; + (Neon_Low4S node:$LHS), node:$RHS)>>; def : NI_2VEL2_laneq(subop # "_4s8h"), neon_uimm3_bare, !cast(op # "_4s"), VPR128Lo, v4i32, v8i16, v8i16, v4i16, Neon_High8H, BinOpFrag<(Neon_vduplane - (Neon_low8H node:$LHS), node:$RHS)>>; + (Neon_Low8H node:$LHS), node:$RHS)>>; def : NI_2VEL2_laneq(subop # "_2d4s"), neon_uimm2_bare, !cast(op # "_2d"), VPR128, v2i64, v4i32, v4i32, v2i32, Neon_High4S, BinOpFrag<(Neon_vduplane - (Neon_low4S node:$LHS), node:$RHS)>>; + (Neon_Low4S node:$LHS), node:$RHS)>>; // Index can only be half of the max value for lane in 64-bit vector diff --git a/test/CodeGen/AArch64/neon-simd-vget.ll b/test/CodeGen/AArch64/neon-simd-vget.ll index f3897032e38..6474499e4ff 100644 --- a/test/CodeGen/AArch64/neon-simd-vget.ll +++ b/test/CodeGen/AArch64/neon-simd-vget.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s define <8 x i8> @test_vget_high_s8(<16 x i8> %a) { -; CHECK: test_vget_high_s8: +; CHECK-LABEL: test_vget_high_s8: ; CHECK: dup d0, {{v[0-9]+}}.d[1] entry: %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> @@ -9,7 +9,7 @@ entry: } define <4 x i16> @test_vget_high_s16(<8 x i16> %a) { -; CHECK: test_vget_high_s16: +; CHECK-LABEL: test_vget_high_s16: ; CHECK: dup d0, {{v[0-9]+}}.d[1] entry: %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> @@ -17,7 +17,7 @@ entry: } define <2 x i32> @test_vget_high_s32(<4 x i32> %a) { -; CHECK: test_vget_high_s32: +; CHECK-LABEL: test_vget_high_s32: ; CHECK: dup d0, {{v[0-9]+}}.d[1] entry: %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> @@ -25,7 +25,7 @@ entry: } define <1 x i64> @test_vget_high_s64(<2 x i64> %a) { -; CHECK: test_vget_high_s64: +; CHECK-LABEL: test_vget_high_s64: ; CHECK: dup d0, {{v[0-9]+}}.d[1] entry: %shuffle.i = shufflevector <2 x i64> %a, <2 x i64> undef, <1 x i32> @@ -33,7 +33,7 @@ entry: } define <8 x i8> @test_vget_high_u8(<16 x i8> %a) { -; CHECK: test_vget_high_u8: +; CHECK-LABEL: test_vget_high_u8: ; CHECK: dup d0, {{v[0-9]+}}.d[1] entry: %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> @@ -41,7 +41,7 @@ entry: } define <4 x i16> @test_vget_high_u16(<8 x i16> %a) { -; CHECK: test_vget_high_u16: +; CHECK-LABEL: test_vget_high_u16: ; CHECK: dup d0, {{v[0-9]+}}.d[1] entry: %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> @@ -49,7 +49,7 @@ entry: } define <2 x i32> @test_vget_high_u32(<4 x i32> %a) { -; CHECK: test_vget_high_u32: +; CHECK-LABEL: test_vget_high_u32: ; CHECK: dup d0, {{v[0-9]+}}.d[1] entry: %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> @@ -57,7 +57,7 @@ entry: } define <1 x i64> @test_vget_high_u64(<2 x i64> %a) { -; CHECK: test_vget_high_u64: +; CHECK-LABEL: test_vget_high_u64: ; CHECK: dup d0, {{v[0-9]+}}.d[1] entry: %shuffle.i = shufflevector <2 x i64> %a, <2 x i64> undef, <1 x i32> @@ -65,7 +65,7 @@ entry: } define <1 x i64> @test_vget_high_p64(<2 x i64> %a) { -; CHECK: test_vget_high_p64: +; CHECK-LABEL: test_vget_high_p64: ; CHECK: dup d0, {{v[0-9]+}}.d[1] entry: %shuffle.i = shufflevector <2 x i64> %a, <2 x i64> undef, <1 x i32> @@ -73,7 +73,7 @@ entry: } define <4 x i16> @test_vget_high_f16(<8 x i16> %a) { -; CHECK: test_vget_high_f16: +; CHECK-LABEL: test_vget_high_f16: ; CHECK: dup d0, {{v[0-9]+}}.d[1] entry: %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> @@ -81,7 +81,7 @@ entry: } define <2 x float> @test_vget_high_f32(<4 x float> %a) { -; CHECK: test_vget_high_f32: +; CHECK-LABEL: test_vget_high_f32: ; CHECK: dup d0, {{v[0-9]+}}.d[1] entry: %shuffle.i = shufflevector <4 x float> %a, <4 x float> undef, <2 x i32> @@ -89,7 +89,7 @@ entry: } define <8 x i8> @test_vget_high_p8(<16 x i8> %a) { -; CHECK: test_vget_high_p8: +; CHECK-LABEL: test_vget_high_p8: ; CHECK: dup d0, {{v[0-9]+}}.d[1] entry: %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> @@ -97,7 +97,7 @@ entry: } define <4 x i16> @test_vget_high_p16(<8 x i16> %a) { -; CHECK: test_vget_high_p16: +; CHECK-LABEL: test_vget_high_p16: ; CHECK: dup d0, {{v[0-9]+}}.d[1] entry: %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> @@ -105,7 +105,7 @@ entry: } define <1 x double> @test_vget_high_f64(<2 x double> %a) { -; CHECK: test_vget_high_f64: +; CHECK-LABEL: test_vget_high_f64: ; CHECK: dup d0, {{v[0-9]+}}.d[1] entry: %shuffle.i = shufflevector <2 x double> %a, <2 x double> undef, <1 x i32> @@ -113,112 +113,112 @@ entry: } define <8 x i8> @test_vget_low_s8(<16 x i8> %a) { -; CHECK: test_vget_low_s8: -; CHECK: dup d0, {{v[0-9]+}}.d[0] +; CHECK-LABEL: test_vget_low_s8: +; CHECK: ret entry: %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> ret <8 x i8> %shuffle.i } define <4 x i16> @test_vget_low_s16(<8 x i16> %a) { -; CHECK: test_vget_low_s16: -; CHECK: dup d0, {{v[0-9]+}}.d[0] +; CHECK-LABEL: test_vget_low_s16: +; CHECK: ret entry: %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> ret <4 x i16> %shuffle.i } define <2 x i32> @test_vget_low_s32(<4 x i32> %a) { -; CHECK: test_vget_low_s32: -; CHECK: dup d0, {{v[0-9]+}}.d[0] +; CHECK-LABEL: test_vget_low_s32: +; CHECK: ret entry: %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> ret <2 x i32> %shuffle.i } define <1 x i64> @test_vget_low_s64(<2 x i64> %a) { -; CHECK: test_vget_low_s64: -; CHECK: dup d0, {{v[0-9]+}}.d[0] +; CHECK-LABEL: test_vget_low_s64: +; CHECK: ret entry: %shuffle.i = shufflevector <2 x i64> %a, <2 x i64> undef, <1 x i32> zeroinitializer ret <1 x i64> %shuffle.i } define <8 x i8> @test_vget_low_u8(<16 x i8> %a) { -; CHECK: test_vget_low_u8: -; CHECK: dup d0, {{v[0-9]+}}.d[0] +; CHECK-LABEL: test_vget_low_u8: +; CHECK: ret entry: %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> ret <8 x i8> %shuffle.i } define <4 x i16> @test_vget_low_u16(<8 x i16> %a) { -; CHECK: test_vget_low_u16: -; CHECK: dup d0, {{v[0-9]+}}.d[0] +; CHECK-LABEL: test_vget_low_u16: +; CHECK: ret entry: %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> ret <4 x i16> %shuffle.i } define <2 x i32> @test_vget_low_u32(<4 x i32> %a) { -; CHECK: test_vget_low_u32: -; CHECK: dup d0, {{v[0-9]+}}.d[0] +; CHECK-LABEL: test_vget_low_u32: +; CHECK: ret entry: %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> ret <2 x i32> %shuffle.i } define <1 x i64> @test_vget_low_u64(<2 x i64> %a) { -; CHECK: test_vget_low_u64: -; CHECK: dup d0, {{v[0-9]+}}.d[0] +; CHECK-LABEL: test_vget_low_u64: +; CHECK: ret entry: %shuffle.i = shufflevector <2 x i64> %a, <2 x i64> undef, <1 x i32> zeroinitializer ret <1 x i64> %shuffle.i } define <1 x i64> @test_vget_low_p64(<2 x i64> %a) { -; CHECK: test_vget_low_p64: -; CHECK: dup d0, {{v[0-9]+}}.d[0] +; CHECK-LABEL: test_vget_low_p64: +; CHECK: ret entry: %shuffle.i = shufflevector <2 x i64> %a, <2 x i64> undef, <1 x i32> zeroinitializer ret <1 x i64> %shuffle.i } define <4 x i16> @test_vget_low_f16(<8 x i16> %a) { -; CHECK: test_vget_low_f16: -; CHECK: dup d0, {{v[0-9]+}}.d[0] +; CHECK-LABEL: test_vget_low_f16: +; CHECK: ret entry: %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> ret <4 x i16> %shuffle.i } define <2 x float> @test_vget_low_f32(<4 x float> %a) { -; CHECK: test_vget_low_f32: -; CHECK: dup d0, {{v[0-9]+}}.d[0] +; CHECK-LABEL: test_vget_low_f32: +; CHECK: ret entry: %shuffle.i = shufflevector <4 x float> %a, <4 x float> undef, <2 x i32> ret <2 x float> %shuffle.i } define <8 x i8> @test_vget_low_p8(<16 x i8> %a) { -; CHECK: test_vget_low_p8: -; CHECK: dup d0, {{v[0-9]+}}.d[0] +; CHECK-LABEL: test_vget_low_p8: +; CHECK: ret entry: %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> ret <8 x i8> %shuffle.i } define <4 x i16> @test_vget_low_p16(<8 x i16> %a) { -; CHECK: test_vget_low_p16: -; CHECK: dup d0, {{v[0-9]+}}.d[0] +; CHECK-LABEL: test_vget_low_p16: +; CHECK: ret entry: %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> ret <4 x i16> %shuffle.i } define <1 x double> @test_vget_low_f64(<2 x double> %a) { -; CHECK: test_vget_low_f64: -; CHECK: dup d0, {{v[0-9]+}}.d[0] +; CHECK-LABEL: test_vget_low_f64: +; CHECK: ret entry: %shuffle.i = shufflevector <2 x double> %a, <2 x double> undef, <1 x i32> zeroinitializer ret <1 x double> %shuffle.i