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add some operations, fix others. should compile several more tests now

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19843 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Lenharth 2005-01-26 01:24:38 +00:00
parent 3576c84baf
commit 0298118cbb
2 changed files with 26 additions and 5 deletions
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17
lib/Target/Alpha/AlphaISelPattern.cpp
View File

@ -50,6 +50,10 @@ namespace {
setOperationAction(ISD::SEXTLOAD , MVT::i8 , Expand);
setOperationAction(ISD::SEXTLOAD , MVT::i16 , Expand);
setOperationAction(ISD::ZERO_EXTEND_INREG, MVT::i1, Expand);
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
computeRegisterProperties();
// addLegalFPImmediate(+0.0); // FLD0
@ -654,9 +658,20 @@ unsigned ISel::SelectExpr(SDOperand N) {
}
case ISD::UREM:
case ISD::SREM:
case ISD::SDIV:
case ISD::UDIV:
//FIXME: alpha really doesn't support any of these operations,
// the ops are expanded into special library calls with
// special calling conventions
switch(N.getOpcode()) {
case UREM: Opc = Alpha::REMQU; break;
case SREM: Opc = Alpha::REMQ; break;
case UDIV: Opc = Alpha::DIVQU; break;
case SDIV: Opc = Alpha::DIVQ; break;
Tmp1 = SelectExpr(N.getOperand(0));
Tmp2 = SelectExpr(N.getOperand(1));
BuildMI(BB, Alpha::REMQU, 2, Result).addReg(Tmp1).addReg(Tmp2);
BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
return Result;
case ISD::SELECT:

14
lib/Target/Alpha/AlphaInstrInfo.td
View File

@ -50,22 +50,28 @@ let isCall = 1,
let isReturn = 1, isTerminator = 1 in
def RETURN : PseudoInstAlpha<(ops ), "ret $$31,($$26),1">; //Return from subroutine
def LOAD_IMM : PseudoInstAlpha<(ops GPRC:$RC, s64imm:$IMM), "ldiq $RC,$IMM">; //Load Immediate Quadword
let Uses = [R28] in
def LOAD_IMM : PseudoInstAlpha<(ops GPRC:$RC, s64imm:$IMM), "ldiq $RC,$IMM">; //Load Immediate Quadword
let Uses = [R29] in
let Uses = [R29, R28] in
def STORE : PseudoInstAlpha<(ops GPRC:$RA, s64imm:$DISP), "stq $RA,$DISP">; //Store quadword
let Uses = [R29] in
let Uses = [R29, R28] in
def LOAD_ADDR : PseudoInstAlpha<(ops GPRC:$RA, s64imm:$DISP), "lda $RA,$DISP">; //Load address
let Uses = [R29] in
let Uses = [R29, R28] in
def LOAD : PseudoInstAlpha<(ops GPRC:$RA, s64imm:$DISP), "ldq $RA,$DISP">; //Load quadword
def LDW : PseudoInstAlpha<(ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldw $RA,$DISP($RB)">; // Load sign-extended word
def LDB : PseudoInstAlpha<(ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldb $RA,$DISP($RB)">; //Load byte
let Uses = [R28, R23, R24, R25, R26] in
{
def REMQU : PseudoInstAlpha<(ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "remqu $RA,$RB,$RC">; //unsigned remander
def REMQ : PseudoInstAlpha<(ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "remq $RA,$RB,$RC">; //unsigned remander
def DIVQU : PseudoInstAlpha<(ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "divqu $RA,$RB,$RC">; //unsigned remander
def DIVQ : PseudoInstAlpha<(ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "divq $RA,$RB,$RC">; //unsigned remander
}
//***********************
//Real instructions