From 02b677594c14e905a07a92472410da18d0fe247e Mon Sep 17 00:00:00 2001 From: Colin LeMahieu Date: Thu, 15 Jan 2015 21:07:52 +0000 Subject: [PATCH] [Hexagon] Updating indexed load-extend patterns and changing test to new expected output. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226206 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Hexagon/HexagonInstrInfo.td | 56 ++++++++----------- .../Hexagon/idxload-with-zero-offset.ll | 40 ++++++------- 2 files changed, 42 insertions(+), 54 deletions(-) diff --git a/lib/Target/Hexagon/HexagonInstrInfo.td b/lib/Target/Hexagon/HexagonInstrInfo.td index a41380e67c4..a6c8e9ee20d 100644 --- a/lib/Target/Hexagon/HexagonInstrInfo.td +++ b/lib/Target/Hexagon/HexagonInstrInfo.td @@ -1558,44 +1558,32 @@ multiclass Loadx_pat; } -def : Pat < (i32 (sextloadi8 ADDRriS11_0:$addr)), - (L2_loadrb_io AddrFI:$addr, 0) >; - -def : Pat < (i32 (zextloadi8 ADDRriS11_0:$addr)), - (L2_loadrub_io AddrFI:$addr, 0) >; - -def : Pat < (i32 (sextloadi16 ADDRriS11_1:$addr)), - (L2_loadrh_io AddrFI:$addr, 0) >; - -def : Pat < (i32 (zextloadi16 ADDRriS11_1:$addr)), - (L2_loadruh_io AddrFI:$addr, 0) >; - -def : Pat < (i32 (load ADDRriS11_2:$addr)), - (L2_loadri_io AddrFI:$addr, 0) >; - -def : Pat < (i64 (load ADDRriS11_3:$addr)), - (L2_loadrd_io AddrFI:$addr, 0) >; - let AddedComplexity = 20 in { -def : Pat < (i32 (sextloadi8 (add IntRegs:$src1, s11_0ExtPred:$offset))), - (L2_loadrb_io IntRegs:$src1, s11_0ExtPred:$offset) >; + defm: Loadx_pat; + defm: Loadx_pat; + defm: Loadx_pat; + defm: Loadx_pat; + defm: Loadx_pat; + defm: Loadx_pat; -def : Pat < (i32 (zextloadi8 (add IntRegs:$src1, s11_0ExtPred:$offset))), - (L2_loadrub_io IntRegs:$src1, s11_0ExtPred:$offset) >; - -def : Pat < (i32 (sextloadi16 (add IntRegs:$src1, s11_1ExtPred:$offset))), - (L2_loadrh_io IntRegs:$src1, s11_1ExtPred:$offset) >; - -def : Pat < (i32 (zextloadi16 (add IntRegs:$src1, s11_1ExtPred:$offset))), - (L2_loadruh_io IntRegs:$src1, s11_1ExtPred:$offset) >; - -def : Pat < (i32 (load (add IntRegs:$src1, s11_2ExtPred:$offset))), - (L2_loadri_io IntRegs:$src1, s11_2ExtPred:$offset) >; - -def : Pat < (i64 (load (add IntRegs:$src1, s11_3ExtPred:$offset))), - (L2_loadrd_io IntRegs:$src1, s11_3ExtPred:$offset) >; + defm: Loadx_pat; + //defm: Loadx_pat; + defm: Loadx_pat; + //defm: Loadx_pat; + defm: Loadx_pat; + defm: Loadx_pat; + defm: Loadx_pat; + defm: Loadx_pat; + // No sextloadi1. } +// Sign-extending loads of i1 need to replicate the lowest bit throughout +// the 32-bit value. Since the loaded value can only be 0 or 1, 0-v should +// do the trick. +let AddedComplexity = 20 in +def: Pat<(i32 (sextloadi1 (i32 IntRegs:$Rs))), + (SUB_ri 0, (L2_loadrub_io IntRegs:$Rs, 0))>; + //===----------------------------------------------------------------------===// // Post increment load //===----------------------------------------------------------------------===// diff --git a/test/CodeGen/Hexagon/idxload-with-zero-offset.ll b/test/CodeGen/Hexagon/idxload-with-zero-offset.ll index 729d79f55a6..fbf1a3a2e4b 100644 --- a/test/CodeGen/Hexagon/idxload-with-zero-offset.ll +++ b/test/CodeGen/Hexagon/idxload-with-zero-offset.ll @@ -1,12 +1,12 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s -; Check that we generate load instruction with (base + register offset << 0) +; RUN: llc -march=hexagon < %s | FileCheck %s +; Check that we generate load instruction with (base + register offset << x) ; load word -define i32 @load_w(i32* nocapture %a, i32 %n) nounwind { -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}<<#0) +define i32 @load_w(i32* nocapture %a, i32 %n, i32 %m) nounwind { +; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}{{ *}}<<{{ *}}#2) entry: - %tmp = shl i32 %n, 4 + %tmp = add i32 %n, %m %scevgep9 = getelementptr i32* %a, i32 %tmp %val = load i32* %scevgep9, align 4 ret i32 %val @@ -14,10 +14,10 @@ entry: ; load unsigned half word -define i16 @load_uh(i16* nocapture %a, i32 %n) nounwind { -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memuh(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}<<#0) +define i16 @load_uh(i16* nocapture %a, i32 %n, i32 %m) nounwind { +; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memuh(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}{{ *}}<<#1) entry: - %tmp = shl i32 %n, 4 + %tmp = add i32 %n, %m %scevgep9 = getelementptr i16* %a, i32 %tmp %val = load i16* %scevgep9, align 2 ret i16 %val @@ -25,10 +25,10 @@ entry: ; load signed half word -define i32 @load_h(i16* nocapture %a, i32 %n) nounwind { -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memh(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}<<#0) +define i32 @load_h(i16* nocapture %a, i32 %n, i32 %m) nounwind { +; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memh(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}{{ *}}<<#1) entry: - %tmp = shl i32 %n, 4 + %tmp = add i32 %n, %m %scevgep9 = getelementptr i16* %a, i32 %tmp %val = load i16* %scevgep9, align 2 %conv = sext i16 %val to i32 @@ -37,10 +37,10 @@ entry: ; load unsigned byte -define i8 @load_ub(i8* nocapture %a, i32 %n) nounwind { -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memub(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}<<#0) +define i8 @load_ub(i8* nocapture %a, i32 %n, i32 %m) nounwind { +; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memub(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}{{ *}}<<#0) entry: - %tmp = shl i32 %n, 4 + %tmp = add i32 %n, %m %scevgep9 = getelementptr i8* %a, i32 %tmp %val = load i8* %scevgep9, align 1 ret i8 %val @@ -48,10 +48,10 @@ entry: ; load signed byte -define i32 @foo_2(i8* nocapture %a, i32 %n) nounwind { -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memb(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}<<#0) +define i32 @foo_2(i8* nocapture %a, i32 %n, i32 %m) nounwind { +; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memb(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}{{ *}}<<{{ *}}#0) entry: - %tmp = shl i32 %n, 4 + %tmp = add i32 %n, %m %scevgep9 = getelementptr i8* %a, i32 %tmp %val = load i8* %scevgep9, align 1 %conv = sext i8 %val to i32 @@ -60,10 +60,10 @@ entry: ; load doubleword -define i64 @load_d(i64* nocapture %a, i32 %n) nounwind { -; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}memd(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}<<#0) +define i64 @load_d(i64* nocapture %a, i32 %n, i32 %m) nounwind { +; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}memd(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}{{ *}}<<{{ *}}#3) entry: - %tmp = shl i32 %n, 4 + %tmp = add i32 %n, %m %scevgep9 = getelementptr i64* %a, i32 %tmp %val = load i64* %scevgep9, align 8 ret i64 %val