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PredicateInstruction returns true if the operation was successful.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37124 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -390,8 +390,8 @@ public:
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}
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/// PredicateInstruction - Convert the instruction into a predicated
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/// instruction.
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virtual void PredicateInstruction(MachineInstr *MI,
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/// instruction. It returns true if the operation was successful.
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virtual bool PredicateInstruction(MachineInstr *MI,
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std::vector<MachineOperand> &Cond) const;
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/// getPointerRegClass - Returns a TargetRegisterClass used for pointer
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@ -423,17 +423,21 @@ ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
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return false;
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}
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void ARMInstrInfo::PredicateInstruction(MachineInstr *MI,
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bool ARMInstrInfo::PredicateInstruction(MachineInstr *MI,
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std::vector<MachineOperand> &Cond) const {
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unsigned Opc = MI->getOpcode();
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if (Opc == ARM::B || Opc == ARM::tB) {
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MI->setInstrDescriptor(get(Opc == ARM::B ? ARM::Bcc : ARM::tBcc));
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MI->addImmOperand(Cond[0].getImmedValue());
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return;
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return true;
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}
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MachineOperand *PMO = MI->findFirstPredOperand();
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PMO->setImm(Cond[0].getImmedValue());
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if (PMO) {
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PMO->setImm(Cond[0].getImmedValue());
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return true;
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}
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return false;
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}
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@ -104,7 +104,7 @@ public:
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virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const;
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// Predication support.
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virtual void PredicateInstruction(MachineInstr *MI,
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virtual bool PredicateInstruction(MachineInstr *MI,
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std::vector<MachineOperand> &Cond) const;
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};
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@ -60,22 +60,27 @@ MachineInstr *TargetInstrInfo::commuteInstruction(MachineInstr *MI) const {
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return MI;
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}
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void TargetInstrInfo::PredicateInstruction(MachineInstr *MI,
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bool TargetInstrInfo::PredicateInstruction(MachineInstr *MI,
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std::vector<MachineOperand> &Cond) const {
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bool MadeChange = false;
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const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
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assert((TID->Flags & M_PREDICABLE) &&
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"Predicating an unpredicable instruction!");
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for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
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if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND)) {
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MachineOperand &MO = MI->getOperand(i);
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if (MO.isReg())
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MO.setReg(Cond[j].getReg());
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else if (MO.isImm())
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MO.setImm(Cond[j].getImmedValue());
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else if (MO.isMBB())
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MO.setMachineBasicBlock(Cond[j].getMachineBasicBlock());
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++j;
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if (TID->Flags & M_PREDICABLE) {
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for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
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if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND)) {
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MachineOperand &MO = MI->getOperand(i);
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if (MO.isReg()) {
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MO.setReg(Cond[j].getReg());
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MadeChange = true;
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} else if (MO.isImm()) {
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MO.setImm(Cond[j].getImmedValue());
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MadeChange = true;
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} else if (MO.isMBB()) {
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MO.setMachineBasicBlock(Cond[j].getMachineBasicBlock());
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MadeChange = true;
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}
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++j;
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}
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}
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}
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return MadeChange;
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}
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