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silence warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31397 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -155,41 +155,6 @@ void ScheduleDAGRRList::CommuteNodesToReducePressure() {
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// Bottom-Up Scheduling
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// Bottom-Up Scheduling
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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static const TargetRegisterClass *getRegClass(SUnit *SU,
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const TargetInstrInfo *TII,
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const MRegisterInfo *MRI,
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SSARegMap *RegMap) {
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if (SU->Node->isTargetOpcode()) {
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unsigned Opc = SU->Node->getTargetOpcode();
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const TargetInstrDescriptor &II = TII->get(Opc);
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return MRI->getRegClass(II.OpInfo->RegClass);
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} else {
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assert(SU->Node->getOpcode() == ISD::CopyFromReg);
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unsigned SrcReg = cast<RegisterSDNode>(SU->Node->getOperand(1))->getReg();
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if (MRegisterInfo::isVirtualRegister(SrcReg))
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return RegMap->getRegClass(SrcReg);
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else {
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for (MRegisterInfo::regclass_iterator I = MRI->regclass_begin(),
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E = MRI->regclass_end(); I != E; ++I)
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if ((*I)->hasType(SU->Node->getValueType(0)) &&
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(*I)->contains(SrcReg))
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return *I;
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assert(false && "Couldn't find register class for reg copy!");
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}
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return NULL;
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}
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}
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static unsigned getNumResults(SUnit *SU) {
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unsigned NumResults = 0;
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for (unsigned i = 0, e = SU->Node->getNumValues(); i != e; ++i) {
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MVT::ValueType VT = SU->Node->getValueType(i);
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if (VT != MVT::Other && VT != MVT::Flag)
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NumResults++;
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}
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return NumResults;
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}
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/// ReleasePred - Decrement the NumSuccsLeft count of a predecessor. Add it to
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/// ReleasePred - Decrement the NumSuccsLeft count of a predecessor. Add it to
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/// the Available queue is the count reaches zero. Also update its cycle bound.
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/// the Available queue is the count reaches zero. Also update its cycle bound.
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void ScheduleDAGRRList::ReleasePred(SUnit *PredSU, bool isChain,
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void ScheduleDAGRRList::ReleasePred(SUnit *PredSU, bool isChain,
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@ -39,15 +39,6 @@ static SDVTList makeVTList(const MVT::ValueType *VTs, unsigned NumVTs) {
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return Res;
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return Res;
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}
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}
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// isInvertibleForFree - Return true if there is no cost to emitting the logical
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// inverse of this node.
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static bool isInvertibleForFree(SDOperand N) {
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if (isa<ConstantSDNode>(N.Val)) return true;
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if (N.Val->getOpcode() == ISD::SETCC && N.Val->hasOneUse())
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return true;
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return false;
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}
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// ConstantFPSDNode Class
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// ConstantFPSDNode Class
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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@ -255,12 +246,6 @@ const TargetMachine &SelectionDAG::getTarget() const {
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// SDNode Profile Support
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// SDNode Profile Support
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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/// getNodeIDOpcode - Return the opcode that has been set for this NodeID.
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///
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static unsigned getNodeIDOpcode(FoldingSetNodeID &ID) {
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return ID.getRawData(0);
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}
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/// AddNodeIDOpcode - Add the node opcode to the NodeID data.
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/// AddNodeIDOpcode - Add the node opcode to the NodeID data.
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///
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///
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static void AddNodeIDOpcode(FoldingSetNodeID &ID, unsigned OpC) {
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static void AddNodeIDOpcode(FoldingSetNodeID &ID, unsigned OpC) {
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