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Hexagon - Add peephole optimizations for zero extends.

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* lib/Target/Hexagon/HexagonInstrInfo.td: Add patterns to combine a
	sequence of a pair of i32->i64 extensions followed by a "bitwise or"
	into COMBINE_rr.
	* lib/Target/Hexagon/HexagonPeephole.cpp: Copy propagate Rx in the
	instruction Rp = COMBINE_Ir_V4(0, Rx) to the uses of Rp:subreg_loreg.
	* test/CodeGen/Hexagon/union-1.ll: New test.
	* test/CodeGen/Hexagon/combine_ir.ll: Fix test.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180946 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Pranav Bhandarkar 2013-05-02 20:22:51 +00:00
parent e2e80cbdcf
commit 02d937d864
4 changed files with 64 additions and 6 deletions
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21
lib/Target/Hexagon/HexagonInstrInfo.td
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@ -2529,6 +2529,27 @@ def : Pat <(i64 (anyext (i1 PredRegs:$src1))),
(i64 (SXTW (i32 (MUX_ii (i1 PredRegs:$src1), 1, 0))))>;
let AddedComplexity = 100 in
def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
(i32 32))),
(i64 (zextloadi32 (i32 (add IntRegs:$src2,
s11_2ExtPred:$offset2)))))),
(i64 (COMBINE_rr (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
(LDriw_indexed IntRegs:$src2,
s11_2ExtPred:$offset2)))>;
def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
(i32 32))),
(i64 (zextloadi32 ADDRriS11_2:$srcLow)))),
(i64 (COMBINE_rr (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
(LDriw ADDRriS11_2:$srcLow)))>;
def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
(i32 32))),
(i64 (zext (i32 IntRegs:$srcLow))))),
(i64 (COMBINE_rr (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
IntRegs:$srcLow))>;
let AddedComplexity = 100 in
def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
(i32 32))),

19
lib/Target/Hexagon/HexagonPeephole.cpp
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@ -73,6 +73,10 @@ static cl::opt<bool> DisableOptSZExt("disable-hexagon-optszext",
cl::Hidden, cl::ZeroOrMore, cl::init(false),
cl::desc("Disable Optimization of Sign/Zero Extends"));
static cl::opt<bool> DisableOptExtTo64("disable-hexagon-opt-ext-to-64",
cl::Hidden, cl::ZeroOrMore, cl::init(false),
cl::desc("Disable Optimization of extensions to i64."));
namespace {
struct HexagonPeephole : public MachineFunctionPass {
const HexagonInstrInfo *QII;
@ -142,6 +146,21 @@ bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) {
}
}
// Look for %vreg170<def> = COMBINE_ir_V4 (0, %vreg169)
// %vreg170:DoublRegs, %vreg169:IntRegs
if (!DisableOptExtTo64 &&
MI->getOpcode () == Hexagon::COMBINE_Ir_V4) {
assert (MI->getNumOperands() == 3);
MachineOperand &Dst = MI->getOperand(0);
MachineOperand &Src1 = MI->getOperand(1);
MachineOperand &Src2 = MI->getOperand(2);
if (Src1.getImm() != 0)
continue;
unsigned DstReg = Dst.getReg();
unsigned SrcReg = Src2.getReg();
PeepholeMap[DstReg] = SrcReg;
}
// Look for this sequence below
// %vregDoubleReg1 = LSRd_ri %vregDoubleReg0, 32
// %vregIntReg = COPY %vregDoubleReg1:subreg_loreg.

7
test/CodeGen/Hexagon/combine_ir.ll
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@ -6,12 +6,7 @@ define void @word(i32* nocapture %a) nounwind {
entry:
%0 = load i32* %a, align 4, !tbaa !0
%1 = zext i32 %0 to i64
%add.ptr = getelementptr inbounds i32* %a, i32 1
%2 = load i32* %add.ptr, align 4, !tbaa !0
%3 = zext i32 %2 to i64
%4 = shl nuw i64 %3, 32
%ins = or i64 %4, %1
tail call void @bar(i64 %ins) nounwind
tail call void @bar(i64 %1) nounwind
ret void
}

23
test/CodeGen/Hexagon/union-1.ll Normal file
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@ -0,0 +1,23 @@
; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
; CHECK: word
; CHECK-NOT: combine(#0
; CHECK: jump bar
define void @word(i32* nocapture %a) nounwind {
entry:
%0 = load i32* %a, align 4, !tbaa !0
%1 = zext i32 %0 to i64
%add.ptr = getelementptr inbounds i32* %a, i32 1
%2 = load i32* %add.ptr, align 4, !tbaa !0
%3 = zext i32 %2 to i64
%4 = shl nuw i64 %3, 32
%ins = or i64 %4, %1
tail call void @bar(i64 %ins) nounwind
ret void
}
declare void @bar(i64)
!0 = metadata !{metadata !"int", metadata !1}
!1 = metadata !{metadata !"omnipotent char", metadata !2}
!2 = metadata !{metadata !"Simple C/C++ TBAA"}