mirror of
https://github.com/c64scene-ar/llvm-6502.git
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[mips][msa] Correct definition of bins[lr] and CHECK-DAG-ize related tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193695 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders
parent
d3b64efcb3
commit
02fbffd4e8
@ -566,13 +566,17 @@ def int_mips_bclri_d : GCCBuiltin<"__builtin_msa_bclri_d">,
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Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_mips_binsl_b : GCCBuiltin<"__builtin_msa_binsl_b">,
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Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
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Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty],
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[IntrNoMem]>;
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def int_mips_binsl_h : GCCBuiltin<"__builtin_msa_binsl_h">,
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Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>;
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Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty],
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[IntrNoMem]>;
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def int_mips_binsl_w : GCCBuiltin<"__builtin_msa_binsl_w">,
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Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
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Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
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[IntrNoMem]>;
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def int_mips_binsl_d : GCCBuiltin<"__builtin_msa_binsl_d">,
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Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], [IntrNoMem]>;
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Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty, llvm_v2i64_ty],
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[IntrNoMem]>;
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def int_mips_binsli_b : GCCBuiltin<"__builtin_msa_binsli_b">,
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Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty, llvm_i32_ty],
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@ -588,13 +592,17 @@ def int_mips_binsli_d : GCCBuiltin<"__builtin_msa_binsli_d">,
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[IntrNoMem]>;
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def int_mips_binsr_b : GCCBuiltin<"__builtin_msa_binsr_b">,
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Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
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Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty],
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[IntrNoMem]>;
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def int_mips_binsr_h : GCCBuiltin<"__builtin_msa_binsr_h">,
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Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>;
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Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty],
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[IntrNoMem]>;
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def int_mips_binsr_w : GCCBuiltin<"__builtin_msa_binsr_w">,
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Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
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Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
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[IntrNoMem]>;
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def int_mips_binsr_d : GCCBuiltin<"__builtin_msa_binsr_d">,
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Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], [IntrNoMem]>;
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Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty, llvm_v2i64_ty],
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[IntrNoMem]>;
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def int_mips_binsri_b : GCCBuiltin<"__builtin_msa_binsri_b">,
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Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty, llvm_i32_ty],
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@ -1258,6 +1258,19 @@ class MSA_3R_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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InstrItinClass Itinerary = itin;
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}
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class MSA_3R_BINSX_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
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RegisterOperand ROWT = ROWD,
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InstrItinClass itin = NoItinerary> {
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dag OutOperandList = (outs ROWD:$wd);
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dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt);
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string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
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list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws,
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ROWT:$wt))];
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string Constraints = "$wd = $wd_in";
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InstrItinClass Itinerary = itin;
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}
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class MSA_3R_SPLAT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
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InstrItinClass itin = NoItinerary> {
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@ -1518,20 +1531,28 @@ class BCLRI_W_DESC : MSA_BIT_W_DESC_BASE<"bclri.w", int_mips_bclri_w,
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class BCLRI_D_DESC : MSA_BIT_D_DESC_BASE<"bclri.d", int_mips_bclri_d,
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MSA128DOpnd>;
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class BINSL_B_DESC : MSA_3R_DESC_BASE<"binsl.b", int_mips_binsl_b, MSA128BOpnd>;
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class BINSL_H_DESC : MSA_3R_DESC_BASE<"binsl.h", int_mips_binsl_h, MSA128HOpnd>;
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class BINSL_W_DESC : MSA_3R_DESC_BASE<"binsl.w", int_mips_binsl_w, MSA128WOpnd>;
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class BINSL_D_DESC : MSA_3R_DESC_BASE<"binsl.d", int_mips_binsl_d, MSA128DOpnd>;
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class BINSL_B_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.b", int_mips_binsl_b,
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MSA128BOpnd>;
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class BINSL_H_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.h", int_mips_binsl_h,
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MSA128HOpnd>;
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class BINSL_W_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.w", int_mips_binsl_w,
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MSA128WOpnd>;
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class BINSL_D_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.d", int_mips_binsl_d,
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MSA128DOpnd>;
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class BINSLI_B_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.b", v16i8, MSA128BOpnd>;
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class BINSLI_H_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.h", v8i16, MSA128HOpnd>;
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class BINSLI_W_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.w", v4i32, MSA128WOpnd>;
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class BINSLI_D_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.d", v2i64, MSA128DOpnd>;
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class BINSR_B_DESC : MSA_3R_DESC_BASE<"binsr.b", int_mips_binsr_b, MSA128BOpnd>;
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class BINSR_H_DESC : MSA_3R_DESC_BASE<"binsr.h", int_mips_binsr_h, MSA128HOpnd>;
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class BINSR_W_DESC : MSA_3R_DESC_BASE<"binsr.w", int_mips_binsr_w, MSA128WOpnd>;
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class BINSR_D_DESC : MSA_3R_DESC_BASE<"binsr.d", int_mips_binsr_d, MSA128DOpnd>;
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class BINSR_B_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.b", int_mips_binsr_b,
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MSA128BOpnd>;
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class BINSR_H_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.h", int_mips_binsr_h,
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MSA128HOpnd>;
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class BINSR_W_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.w", int_mips_binsr_w,
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MSA128WOpnd>;
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class BINSR_D_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.d", int_mips_binsr_d,
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MSA128DOpnd>;
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class BINSRI_B_DESC : MSA_BIT_BINSRI_DESC_BASE<"binsri.b", v16i8, MSA128BOpnd>;
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class BINSRI_H_DESC : MSA_BIT_BINSRI_DESC_BASE<"binsri.h", v8i16, MSA128HOpnd>;
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@ -90,183 +90,231 @@ declare <2 x i64> @llvm.mips.bclr.d(<2 x i64>, <2 x i64>) nounwind
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; CHECK: bclr.d
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; CHECK: st.d
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; CHECK: .size llvm_mips_bclr_d_test
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;
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@llvm_mips_binsl_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
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@llvm_mips_binsl_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
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@llvm_mips_binsl_b_ARG2 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
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@llvm_mips_binsl_b_ARG3 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
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@llvm_mips_binsl_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
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define void @llvm_mips_binsl_b_test() nounwind {
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entry:
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%0 = load <16 x i8>* @llvm_mips_binsl_b_ARG1
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%1 = load <16 x i8>* @llvm_mips_binsl_b_ARG2
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%2 = tail call <16 x i8> @llvm.mips.binsl.b(<16 x i8> %0, <16 x i8> %1)
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store <16 x i8> %2, <16 x i8>* @llvm_mips_binsl_b_RES
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%2 = load <16 x i8>* @llvm_mips_binsl_b_ARG3
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%3 = tail call <16 x i8> @llvm.mips.binsl.b(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2)
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store <16 x i8> %3, <16 x i8>* @llvm_mips_binsl_b_RES
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ret void
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}
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declare <16 x i8> @llvm.mips.binsl.b(<16 x i8>, <16 x i8>) nounwind
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declare <16 x i8> @llvm.mips.binsl.b(<16 x i8>, <16 x i8>, <16 x i8>) nounwind
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; CHECK: llvm_mips_binsl_b_test:
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; CHECK: ld.b
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; CHECK: ld.b
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; CHECK: binsl.b
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; CHECK: st.b
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; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_binsl_b_ARG1)(
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; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_binsl_b_ARG2)(
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; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_binsl_b_ARG3)(
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; CHECK-DAG: ld.b [[R4:\$w[0-9]+]], 0([[R1]])
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; CHECK-DAG: ld.b [[R5:\$w[0-9]+]], 0([[R2]])
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; CHECK-DAG: ld.b [[R6:\$w[0-9]+]], 0([[R3]])
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; CHECK-DAG: binsl.b [[R4]], [[R5]], [[R6]]
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; CHECK-DAG: st.b [[R4]], 0(
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; CHECK: .size llvm_mips_binsl_b_test
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;
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@llvm_mips_binsl_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
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@llvm_mips_binsl_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
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@llvm_mips_binsl_h_ARG2 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
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@llvm_mips_binsl_h_ARG3 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
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@llvm_mips_binsl_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
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define void @llvm_mips_binsl_h_test() nounwind {
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entry:
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%0 = load <8 x i16>* @llvm_mips_binsl_h_ARG1
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%1 = load <8 x i16>* @llvm_mips_binsl_h_ARG2
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%2 = tail call <8 x i16> @llvm.mips.binsl.h(<8 x i16> %0, <8 x i16> %1)
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store <8 x i16> %2, <8 x i16>* @llvm_mips_binsl_h_RES
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%2 = load <8 x i16>* @llvm_mips_binsl_h_ARG3
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%3 = tail call <8 x i16> @llvm.mips.binsl.h(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2)
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store <8 x i16> %3, <8 x i16>* @llvm_mips_binsl_h_RES
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ret void
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}
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declare <8 x i16> @llvm.mips.binsl.h(<8 x i16>, <8 x i16>) nounwind
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declare <8 x i16> @llvm.mips.binsl.h(<8 x i16>, <8 x i16>, <8 x i16>) nounwind
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; CHECK: llvm_mips_binsl_h_test:
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; CHECK: ld.h
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; CHECK: ld.h
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; CHECK: binsl.h
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; CHECK: st.h
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; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_binsl_h_ARG1)(
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; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_binsl_h_ARG2)(
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; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_binsl_h_ARG3)(
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; CHECK-DAG: ld.h [[R4:\$w[0-9]+]], 0([[R1]])
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; CHECK-DAG: ld.h [[R5:\$w[0-9]+]], 0([[R2]])
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; CHECK-DAG: ld.h [[R6:\$w[0-9]+]], 0([[R3]])
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; CHECK-DAG: binsl.h [[R4]], [[R5]], [[R6]]
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; CHECK-DAG: st.h [[R4]], 0(
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; CHECK: .size llvm_mips_binsl_h_test
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;
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@llvm_mips_binsl_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
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@llvm_mips_binsl_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
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@llvm_mips_binsl_w_ARG2 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
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@llvm_mips_binsl_w_ARG3 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
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@llvm_mips_binsl_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
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define void @llvm_mips_binsl_w_test() nounwind {
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entry:
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%0 = load <4 x i32>* @llvm_mips_binsl_w_ARG1
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%1 = load <4 x i32>* @llvm_mips_binsl_w_ARG2
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%2 = tail call <4 x i32> @llvm.mips.binsl.w(<4 x i32> %0, <4 x i32> %1)
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store <4 x i32> %2, <4 x i32>* @llvm_mips_binsl_w_RES
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%2 = load <4 x i32>* @llvm_mips_binsl_w_ARG3
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%3 = tail call <4 x i32> @llvm.mips.binsl.w(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2)
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store <4 x i32> %3, <4 x i32>* @llvm_mips_binsl_w_RES
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ret void
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}
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declare <4 x i32> @llvm.mips.binsl.w(<4 x i32>, <4 x i32>) nounwind
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declare <4 x i32> @llvm.mips.binsl.w(<4 x i32>, <4 x i32>, <4 x i32>) nounwind
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; CHECK: llvm_mips_binsl_w_test:
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; CHECK: ld.w
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; CHECK: ld.w
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; CHECK: binsl.w
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; CHECK: st.w
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; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_binsl_w_ARG1)(
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; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_binsl_w_ARG2)(
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; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_binsl_w_ARG3)(
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; CHECK-DAG: ld.w [[R4:\$w[0-9]+]], 0([[R1]])
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; CHECK-DAG: ld.w [[R5:\$w[0-9]+]], 0([[R2]])
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; CHECK-DAG: ld.w [[R6:\$w[0-9]+]], 0([[R3]])
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; CHECK-DAG: binsl.w [[R4]], [[R5]], [[R6]]
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; CHECK-DAG: st.w [[R4]], 0(
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; CHECK: .size llvm_mips_binsl_w_test
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;
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@llvm_mips_binsl_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
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@llvm_mips_binsl_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16
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@llvm_mips_binsl_d_ARG2 = global <2 x i64> <i64 0, i64 1>, align 16
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@llvm_mips_binsl_d_ARG3 = global <2 x i64> <i64 2, i64 3>, align 16
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@llvm_mips_binsl_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
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define void @llvm_mips_binsl_d_test() nounwind {
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entry:
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%0 = load <2 x i64>* @llvm_mips_binsl_d_ARG1
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%1 = load <2 x i64>* @llvm_mips_binsl_d_ARG2
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%2 = tail call <2 x i64> @llvm.mips.binsl.d(<2 x i64> %0, <2 x i64> %1)
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store <2 x i64> %2, <2 x i64>* @llvm_mips_binsl_d_RES
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%2 = load <2 x i64>* @llvm_mips_binsl_d_ARG3
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%3 = tail call <2 x i64> @llvm.mips.binsl.d(<2 x i64> %0, <2 x i64> %1, <2 x i64> %2)
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store <2 x i64> %3, <2 x i64>* @llvm_mips_binsl_d_RES
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ret void
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}
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declare <2 x i64> @llvm.mips.binsl.d(<2 x i64>, <2 x i64>) nounwind
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declare <2 x i64> @llvm.mips.binsl.d(<2 x i64>, <2 x i64>, <2 x i64>) nounwind
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; CHECK: llvm_mips_binsl_d_test:
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; CHECK: ld.d
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; CHECK: ld.d
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; CHECK: binsl.d
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; CHECK: st.d
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; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_binsl_d_ARG1)(
|
||||
; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_binsl_d_ARG2)(
|
||||
; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_binsl_d_ARG3)(
|
||||
; CHECK-DAG: ld.d [[R4:\$w[0-9]+]], 0([[R1]])
|
||||
; CHECK-DAG: ld.d [[R5:\$w[0-9]+]], 0([[R2]])
|
||||
; CHECK-DAG: ld.d [[R6:\$w[0-9]+]], 0([[R3]])
|
||||
; CHECK-DAG: binsl.d [[R4]], [[R5]], [[R6]]
|
||||
; CHECK-DAG: st.d [[R4]], 0(
|
||||
; CHECK: .size llvm_mips_binsl_d_test
|
||||
;
|
||||
|
||||
@llvm_mips_binsr_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
|
||||
@llvm_mips_binsr_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
|
||||
@llvm_mips_binsr_b_ARG2 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
|
||||
@llvm_mips_binsr_b_ARG3 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
|
||||
@llvm_mips_binsr_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
|
||||
|
||||
define void @llvm_mips_binsr_b_test() nounwind {
|
||||
entry:
|
||||
%0 = load <16 x i8>* @llvm_mips_binsr_b_ARG1
|
||||
%1 = load <16 x i8>* @llvm_mips_binsr_b_ARG2
|
||||
%2 = tail call <16 x i8> @llvm.mips.binsr.b(<16 x i8> %0, <16 x i8> %1)
|
||||
store <16 x i8> %2, <16 x i8>* @llvm_mips_binsr_b_RES
|
||||
%2 = load <16 x i8>* @llvm_mips_binsr_b_ARG3
|
||||
%3 = tail call <16 x i8> @llvm.mips.binsr.b(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2)
|
||||
store <16 x i8> %3, <16 x i8>* @llvm_mips_binsr_b_RES
|
||||
ret void
|
||||
}
|
||||
|
||||
declare <16 x i8> @llvm.mips.binsr.b(<16 x i8>, <16 x i8>) nounwind
|
||||
declare <16 x i8> @llvm.mips.binsr.b(<16 x i8>, <16 x i8>, <16 x i8>) nounwind
|
||||
|
||||
; CHECK: llvm_mips_binsr_b_test:
|
||||
; CHECK: ld.b
|
||||
; CHECK: ld.b
|
||||
; CHECK: binsr.b
|
||||
; CHECK: st.b
|
||||
; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_binsr_b_ARG1)(
|
||||
; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_binsr_b_ARG2)(
|
||||
; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_binsr_b_ARG3)(
|
||||
; CHECK-DAG: ld.b [[R4:\$w[0-9]+]], 0([[R1]])
|
||||
; CHECK-DAG: ld.b [[R5:\$w[0-9]+]], 0([[R2]])
|
||||
; CHECK-DAG: ld.b [[R6:\$w[0-9]+]], 0([[R3]])
|
||||
; CHECK-DAG: binsr.b [[R4]], [[R5]], [[R6]]
|
||||
; CHECK-DAG: st.b [[R4]], 0(
|
||||
; CHECK: .size llvm_mips_binsr_b_test
|
||||
;
|
||||
|
||||
@llvm_mips_binsr_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
|
||||
@llvm_mips_binsr_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
|
||||
@llvm_mips_binsr_h_ARG2 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
|
||||
@llvm_mips_binsr_h_ARG3 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
|
||||
@llvm_mips_binsr_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
|
||||
|
||||
define void @llvm_mips_binsr_h_test() nounwind {
|
||||
entry:
|
||||
%0 = load <8 x i16>* @llvm_mips_binsr_h_ARG1
|
||||
%1 = load <8 x i16>* @llvm_mips_binsr_h_ARG2
|
||||
%2 = tail call <8 x i16> @llvm.mips.binsr.h(<8 x i16> %0, <8 x i16> %1)
|
||||
store <8 x i16> %2, <8 x i16>* @llvm_mips_binsr_h_RES
|
||||
%2 = load <8 x i16>* @llvm_mips_binsr_h_ARG3
|
||||
%3 = tail call <8 x i16> @llvm.mips.binsr.h(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2)
|
||||
store <8 x i16> %3, <8 x i16>* @llvm_mips_binsr_h_RES
|
||||
ret void
|
||||
}
|
||||
|
||||
declare <8 x i16> @llvm.mips.binsr.h(<8 x i16>, <8 x i16>) nounwind
|
||||
declare <8 x i16> @llvm.mips.binsr.h(<8 x i16>, <8 x i16>, <8 x i16>) nounwind
|
||||
|
||||
; CHECK: llvm_mips_binsr_h_test:
|
||||
; CHECK: ld.h
|
||||
; CHECK: ld.h
|
||||
; CHECK: binsr.h
|
||||
; CHECK: st.h
|
||||
; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_binsr_h_ARG1)(
|
||||
; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_binsr_h_ARG2)(
|
||||
; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_binsr_h_ARG3)(
|
||||
; CHECK-DAG: ld.h [[R4:\$w[0-9]+]], 0([[R1]])
|
||||
; CHECK-DAG: ld.h [[R5:\$w[0-9]+]], 0([[R2]])
|
||||
; CHECK-DAG: ld.h [[R6:\$w[0-9]+]], 0([[R3]])
|
||||
; CHECK-DAG: binsr.h [[R4]], [[R5]], [[R6]]
|
||||
; CHECK-DAG: st.h [[R4]], 0(
|
||||
; CHECK: .size llvm_mips_binsr_h_test
|
||||
;
|
||||
|
||||
@llvm_mips_binsr_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
|
||||
@llvm_mips_binsr_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
|
||||
@llvm_mips_binsr_w_ARG2 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
|
||||
@llvm_mips_binsr_w_ARG3 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
|
||||
@llvm_mips_binsr_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
|
||||
|
||||
define void @llvm_mips_binsr_w_test() nounwind {
|
||||
entry:
|
||||
%0 = load <4 x i32>* @llvm_mips_binsr_w_ARG1
|
||||
%1 = load <4 x i32>* @llvm_mips_binsr_w_ARG2
|
||||
%2 = tail call <4 x i32> @llvm.mips.binsr.w(<4 x i32> %0, <4 x i32> %1)
|
||||
store <4 x i32> %2, <4 x i32>* @llvm_mips_binsr_w_RES
|
||||
%2 = load <4 x i32>* @llvm_mips_binsr_w_ARG3
|
||||
%3 = tail call <4 x i32> @llvm.mips.binsr.w(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2)
|
||||
store <4 x i32> %3, <4 x i32>* @llvm_mips_binsr_w_RES
|
||||
ret void
|
||||
}
|
||||
|
||||
declare <4 x i32> @llvm.mips.binsr.w(<4 x i32>, <4 x i32>) nounwind
|
||||
declare <4 x i32> @llvm.mips.binsr.w(<4 x i32>, <4 x i32>, <4 x i32>) nounwind
|
||||
|
||||
; CHECK: llvm_mips_binsr_w_test:
|
||||
; CHECK: ld.w
|
||||
; CHECK: ld.w
|
||||
; CHECK: binsr.w
|
||||
; CHECK: st.w
|
||||
; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_binsr_w_ARG1)(
|
||||
; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_binsr_w_ARG2)(
|
||||
; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_binsr_w_ARG3)(
|
||||
; CHECK-DAG: ld.w [[R4:\$w[0-9]+]], 0([[R1]])
|
||||
; CHECK-DAG: ld.w [[R5:\$w[0-9]+]], 0([[R2]])
|
||||
; CHECK-DAG: ld.w [[R6:\$w[0-9]+]], 0([[R3]])
|
||||
; CHECK-DAG: binsr.w [[R4]], [[R5]], [[R6]]
|
||||
; CHECK-DAG: st.w [[R4]], 0(
|
||||
; CHECK: .size llvm_mips_binsr_w_test
|
||||
;
|
||||
|
||||
@llvm_mips_binsr_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
|
||||
@llvm_mips_binsr_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16
|
||||
@llvm_mips_binsr_d_ARG2 = global <2 x i64> <i64 0, i64 1>, align 16
|
||||
@llvm_mips_binsr_d_ARG3 = global <2 x i64> <i64 2, i64 3>, align 16
|
||||
@llvm_mips_binsr_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
|
||||
|
||||
define void @llvm_mips_binsr_d_test() nounwind {
|
||||
entry:
|
||||
%0 = load <2 x i64>* @llvm_mips_binsr_d_ARG1
|
||||
%1 = load <2 x i64>* @llvm_mips_binsr_d_ARG2
|
||||
%2 = tail call <2 x i64> @llvm.mips.binsr.d(<2 x i64> %0, <2 x i64> %1)
|
||||
store <2 x i64> %2, <2 x i64>* @llvm_mips_binsr_d_RES
|
||||
%2 = load <2 x i64>* @llvm_mips_binsr_d_ARG3
|
||||
%3 = tail call <2 x i64> @llvm.mips.binsr.d(<2 x i64> %0, <2 x i64> %1, <2 x i64> %2)
|
||||
store <2 x i64> %3, <2 x i64>* @llvm_mips_binsr_d_RES
|
||||
ret void
|
||||
}
|
||||
|
||||
declare <2 x i64> @llvm.mips.binsr.d(<2 x i64>, <2 x i64>) nounwind
|
||||
declare <2 x i64> @llvm.mips.binsr.d(<2 x i64>, <2 x i64>, <2 x i64>) nounwind
|
||||
|
||||
; CHECK: llvm_mips_binsr_d_test:
|
||||
; CHECK: ld.d
|
||||
; CHECK: ld.d
|
||||
; CHECK: binsr.d
|
||||
; CHECK: st.d
|
||||
; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_binsr_d_ARG1)(
|
||||
; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_binsr_d_ARG2)(
|
||||
; CHECK-DAG: lw [[R3:\$[0-9]+]], %got(llvm_mips_binsr_d_ARG3)(
|
||||
; CHECK-DAG: ld.d [[R4:\$w[0-9]+]], 0([[R1]])
|
||||
; CHECK-DAG: ld.d [[R5:\$w[0-9]+]], 0([[R2]])
|
||||
; CHECK-DAG: ld.d [[R6:\$w[0-9]+]], 0([[R3]])
|
||||
; CHECK-DAG: binsr.d [[R4]], [[R5]], [[R6]]
|
||||
; CHECK-DAG: st.d [[R4]], 0(
|
||||
; CHECK: .size llvm_mips_binsr_d_test
|
||||
;
|
||||
|
||||
@llvm_mips_bneg_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
|
||||
@llvm_mips_bneg_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
|
||||
@llvm_mips_bneg_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
|
||||
|
||||
Loading…
Reference in New Issue
Block a user