Rename SetCCResultContents to BooleanContents. In

practice these booleans are mostly produced by SetCC,
however the concept is more general.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59911 91177308-0d34-0410-b5e6-96231b3b80d8

include/llvm/CodeGen/SelectionDAGNodes.h

@@ -255,7 +255,7 @@ namespace ISD {
     // produce two results: the normal result of the add, and a boolean that
     // indicates if an overflow occured (*not* a flag, because it may be stored
     // to memory, etc.).  If the type of the boolean is not i1 then the high
-    // bits conform to getSetCCResultContents.
+    // bits conform to getBooleanContents.
     // These nodes are generated from the llvm.[su]add.with.overflow intrinsics.
     SADDO, UADDO,
 
@@ -336,7 +336,7 @@ namespace ISD {
     CTTZ, CTLZ, CTPOP,
 
     // Select(COND, TRUEVAL, FALSEVAL).  If the type of the boolean COND is not
-    // i1 then the high bits must conform to getSetCCResultContents.
+    // i1 then the high bits must conform to getBooleanContents.
     SELECT,
 
     // Select with condition operator - This selects between a true value and 
@@ -347,7 +347,7 @@ namespace ISD {
 
     // SetCC operator - This evaluates to a true value iff the condition is
     // true.  If the result value type is not i1 then the high bits conform
-    // to getSetCCResultContents.  The operands to this are the left and right
+    // to getBooleanContents.  The operands to this are the left and right
     // operands to compare (ops #0, and #1) and the condition code to compare
     // them with (op #2) as a CondCodeSDNode.
     SETCC,
@@ -494,7 +494,7 @@ namespace ISD {
     // BRCOND - Conditional branch.  The first operand is the chain, the
     // second is the condition, the third is the block to branch to if the
     // condition is true.  If the type of the condition is not i1, then the
-    // high bits must conform to getSetCCResultContents.
+    // high bits must conform to getBooleanContents.
     BRCOND,
 
     // BR_CC - Conditional branch.  The behavior is like that of SELECT_CC, in

include/llvm/Target/TargetLowering.h

@@ -78,10 +78,10 @@ public:
     Extend      // Oversized shift pulls in zeros or sign bits.
   };
 
-  enum SetCCResultValue {
-    UndefinedSetCCResult,          // SetCC returns a garbage/unknown extend.
-    ZeroOrOneSetCCResult,          // SetCC returns a zero extended result.
-    ZeroOrNegativeOneSetCCResult   // SetCC returns a sign extended result.
+  enum BooleanContent { // How the target represents true/false values.
+    UndefinedBooleanContent,    // Only bit 0 counts, the rest can hold garbage.
+    ZeroOrOneBooleanContent,        // All bits zero except for bit 0.
+    ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
   };
 
   enum SchedPreference {
@@ -121,10 +121,12 @@ public:
   /// operations.
   virtual MVT getSetCCResultType(const SDValue &) const;
 
-  /// getSetCCResultContents - For targets without boolean registers, this flag
-  /// returns information about the contents of the high-bits in the setcc
-  /// result register.
-  SetCCResultValue getSetCCResultContents() const { return SetCCResultContents;}
+  /// getBooleanContents - For targets without i1 registers, this gives the
+  /// nature of the high-bits of boolean values held in types wider than i1.
+  /// "Boolean values" are special true/false values produced by nodes like
+  /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
+  /// Not to be confused with general values promoted from i1.
+  BooleanContent getBooleanContents() const { return BooleanContents;}
 
   /// getSchedulingPreference - Return target scheduling preference.
   SchedPreference getSchedulingPreference() const {
@@ -812,9 +814,9 @@ protected:
   /// amounts.  This type defaults to the pointer type.
   void setShiftAmountType(MVT VT) { ShiftAmountTy = VT; }
 
-  /// setSetCCResultContents - Specify how the target extends the result of a
-  /// setcc operation in a register.
-  void setSetCCResultContents(SetCCResultValue Ty) { SetCCResultContents = Ty; }
+  /// setBooleanContents - Specify how the target extends the result of a
+  /// boolean value from i1 to a wider type.  See getBooleanContents.
+  void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; }
 
   /// setSchedulingPreference - Specify the target scheduling preference.
   void setSchedulingPreference(SchedPreference Pref) {
@@ -1430,9 +1432,9 @@ private:
 
   OutOfRangeShiftAmount ShiftAmtHandling;
 
-  /// SetCCResultContents - Information about the contents of the high-bits in
-  /// the result of a setcc comparison operation.
-  SetCCResultValue SetCCResultContents;
+  /// BooleanContents - Information about the contents of the high-bits in
+  /// boolean values held in a type wider than i1.  See getBooleanContents.
+  BooleanContent BooleanContents;
 
   /// SchedPreferenceInfo - The target scheduling preference: shortest possible
   /// total cycles or lowest register usage.

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

@@ -5444,7 +5444,7 @@ SDValue DAGCombiner::SimplifySelectCC(SDValue N0, SDValue N1,
   
   // fold select C, 16, 0 -> shl C, 4
   if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() &&
-      TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) {
+      TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent) {
     
     // If the caller doesn't want us to simplify this into a zext of a compare,
     // don't do it.

lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

@@ -698,19 +698,19 @@ SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
   SDValue Cond = GetPromotedInteger(N->getOperand(1));  // Promote condition.
 
   // Make sure the extra bits coming from type promotion conform to
-  // getSetCCResultContents.
+  // getBooleanContents.
   unsigned CondBits = Cond.getValueSizeInBits();
-  switch (TLI.getSetCCResultContents()) {
+  switch (TLI.getBooleanContents()) {
   default:
-    assert(false && "Unknown SetCCResultValue!");
-  case TargetLowering::UndefinedSetCCResult:
+    assert(false && "Unknown BooleanContent!");
+  case TargetLowering::UndefinedBooleanContent:
     // The promoted value, which may contain rubbish in the upper bits, is fine.
     break;
-  case TargetLowering::ZeroOrOneSetCCResult:
+  case TargetLowering::ZeroOrOneBooleanContent:
     if (!DAG.MaskedValueIsZero(Cond,APInt::getHighBitsSet(CondBits,CondBits-1)))
       Cond = DAG.getZeroExtendInReg(Cond, MVT::i1);
     break;
-  case TargetLowering::ZeroOrNegativeOneSetCCResult:
+  case TargetLowering::ZeroOrNegativeOneBooleanContent:
     if (DAG.ComputeNumSignBits(Cond) != CondBits)
       Cond = DAG.getNode(ISD::SIGN_EXTEND_INREG, Cond.getValueType(), Cond,
                          DAG.getValueType(MVT::i1));
@@ -830,27 +830,27 @@ SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
   assert(isTypeLegal(SVT) && "Illegal SetCC type!");
   assert(Cond.getValueType().bitsLE(SVT) && "Unexpected SetCC type!");
 
-  // Make sure the extra bits conform to getSetCCResultContents.  There are
+  // Make sure the extra bits conform to getBooleanContents.  There are
   // two sets of extra bits: those in Cond, which come from type promotion,
   // and those we need to add to have the final type be SVT (for most targets
   // this last set of bits is empty).
   unsigned CondBits = Cond.getValueSizeInBits();
   ISD::NodeType ExtendCode;
-  switch (TLI.getSetCCResultContents()) {
+  switch (TLI.getBooleanContents()) {
   default:
-    assert(false && "Unknown SetCCResultValue!");
-  case TargetLowering::UndefinedSetCCResult:
+    assert(false && "Unknown BooleanContent!");
+  case TargetLowering::UndefinedBooleanContent:
     // Extend to SVT by adding rubbish.
     ExtendCode = ISD::ANY_EXTEND;
     break;
-  case TargetLowering::ZeroOrOneSetCCResult:
+  case TargetLowering::ZeroOrOneBooleanContent:
     ExtendCode = ISD::ZERO_EXTEND;
     if (!DAG.MaskedValueIsZero(Cond,APInt::getHighBitsSet(CondBits,CondBits-1)))
       // All extra bits need to be cleared.  Do this by zero extending the
       // original condition value all the way to SVT.
       Cond = N->getOperand(0);
     break;
-  case TargetLowering::ZeroOrNegativeOneSetCCResult: {
+  case TargetLowering::ZeroOrNegativeOneBooleanContent: {
     ExtendCode = ISD::SIGN_EXTEND;
     unsigned SignBits = DAG.ComputeNumSignBits(Cond);
     if (SignBits != CondBits)

lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

@@ -210,8 +210,8 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
   if (NVT.bitsLE(SVT)) {
     // The SETCC result type is bigger than the vector element type.
     // Ensure the SETCC result is sign-extended.
-    if (TLI.getSetCCResultContents() !=
-        TargetLowering::ZeroOrNegativeOneSetCCResult)
+    if (TLI.getBooleanContents() !=
+        TargetLowering::ZeroOrNegativeOneBooleanContent)
       Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, SVT, Res,
                         DAG.getValueType(MVT::i1));
     // Truncate to the final type.
@@ -219,8 +219,8 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
   } else {
     // The SETCC result type is smaller than the vector element type.
     // If the SetCC result is not sign-extended, chop it down to MVT::i1.
-    if (TLI.getSetCCResultContents() !=
-        TargetLowering::ZeroOrNegativeOneSetCCResult)
+    if (TLI.getBooleanContents() !=
+        TargetLowering::ZeroOrNegativeOneBooleanContent)
       Res = DAG.getNode(ISD::TRUNCATE, MVT::i1, Res);
     // Sign extend to the final type.
     return DAG.getNode(ISD::SIGN_EXTEND, NVT, Res);

lib/CodeGen/SelectionDAG/SelectionDAG.cpp

@@ -1495,10 +1495,10 @@ void SelectionDAG::ComputeMaskedBits(SDValue Op, const APInt &Mask,
   case ISD::UADDO:
     if (Op.getResNo() != 1)
       return;
-    // The boolean result conforms to getSetCCResultContents.  Fall through.
+    // The boolean result conforms to getBooleanContents.  Fall through.
   case ISD::SETCC:
     // If we know the result of a setcc has the top bits zero, use this info.
-    if (TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult &&
+    if (TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent &&
         BitWidth > 1)
       KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
     return;
@@ -1903,11 +1903,11 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, unsigned Depth) const{
   case ISD::UADDO:
     if (Op.getResNo() != 1)
       break;
-    // The boolean result conforms to getSetCCResultContents.  Fall through.
+    // The boolean result conforms to getBooleanContents.  Fall through.
   case ISD::SETCC:
     // If setcc returns 0/-1, all bits are sign bits.
-    if (TLI.getSetCCResultContents() ==
-        TargetLowering::ZeroOrNegativeOneSetCCResult)
+    if (TLI.getBooleanContents() ==
+        TargetLowering::ZeroOrNegativeOneBooleanContent)
       return VTBits;
     break;
   case ISD::ROTL:

lib/CodeGen/SelectionDAG/TargetLowering.cpp

@@ -462,7 +462,7 @@ TargetLowering::TargetLowering(TargetMachine &tm)
   StackPointerRegisterToSaveRestore = 0;
   ExceptionPointerRegister = 0;
   ExceptionSelectorRegister = 0;
-  SetCCResultContents = UndefinedSetCCResult;
+  BooleanContents = UndefinedBooleanContent;
   SchedPreferenceInfo = SchedulingForLatency;
   JumpBufSize = 0;
   JumpBufAlignment = 0;

lib/Target/Alpha/AlphaISelLowering.cpp

@@ -41,7 +41,7 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM)
   // Set up the TargetLowering object.
   //I am having problems with shr n ubyte 1
   setShiftAmountType(MVT::i64);
-  setSetCCResultContents(ZeroOrOneSetCCResult);
+  setBooleanContents(ZeroOrOneBooleanContent);
   
   setUsesGlobalOffsetTable(true);
   

lib/Target/CellSPU/SPUISelLowering.cpp

@@ -393,7 +393,7 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM)
   setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
 
   setShiftAmountType(MVT::i32);
-  setSetCCResultContents(ZeroOrOneSetCCResult);
+  setBooleanContents(ZeroOrOneBooleanContent);
 
   setStackPointerRegisterToSaveRestore(SPU::R1);
 

lib/Target/Mips/MipsISelLowering.cpp

@@ -59,7 +59,7 @@ MipsTargetLowering(MipsTargetMachine &TM): TargetLowering(TM)
 
   // Mips does not have i1 type, so use i32 for
   // setcc operations results (slt, sgt, ...). 
-  setSetCCResultContents(ZeroOrOneSetCCResult);
+  setBooleanContents(ZeroOrOneBooleanContent);
 
   // JumpTable targets must use GOT when using PIC_
   setUsesGlobalOffsetTable(true);

lib/Target/PowerPC/PPCISelLowering.cpp

@@ -341,7 +341,7 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
   }
   
   setShiftAmountType(MVT::i32);
-  setSetCCResultContents(ZeroOrOneSetCCResult);
+  setBooleanContents(ZeroOrOneBooleanContent);
   
   if (TM.getSubtarget<PPCSubtarget>().isPPC64()) {
     setStackPointerRegisterToSaveRestore(PPC::X1);

lib/Target/X86/X86ISelLowering.cpp

@@ -63,7 +63,7 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
 
   // X86 is weird, it always uses i8 for shift amounts and setcc results.
   setShiftAmountType(MVT::i8);
-  setSetCCResultContents(ZeroOrOneSetCCResult);
+  setBooleanContents(ZeroOrOneBooleanContent);
   setSchedulingPreference(SchedulingForRegPressure);
   setShiftAmountFlavor(Mask);   // shl X, 32 == shl X, 0
   setStackPointerRegisterToSaveRestore(X86StackPtr);

lib/Target/XCore/XCoreISelLowering.cpp

@@ -74,7 +74,7 @@ XCoreTargetLowering::XCoreTargetLowering(XCoreTargetMachine &XTM)
   setSchedulingPreference(SchedulingForRegPressure);
 
   // Use i32 for setcc operations results (slt, sgt, ...).
-  setSetCCResultContents(ZeroOrOneSetCCResult);
+  setBooleanContents(ZeroOrOneBooleanContent);
 
   // XCore does not have the NodeTypes below.
   setOperationAction(ISD::BR_CC,     MVT::Other, Expand);