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Rename SetCCResultContents to BooleanContents. In
practice these booleans are mostly produced by SetCC, however the concept is more general. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59911 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -255,7 +255,7 @@ namespace ISD {
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// produce two results: the normal result of the add, and a boolean that
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// indicates if an overflow occured (*not* a flag, because it may be stored
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// to memory, etc.). If the type of the boolean is not i1 then the high
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// bits conform to getSetCCResultContents.
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// bits conform to getBooleanContents.
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// These nodes are generated from the llvm.[su]add.with.overflow intrinsics.
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SADDO, UADDO,
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@ -336,7 +336,7 @@ namespace ISD {
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CTTZ, CTLZ, CTPOP,
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// Select(COND, TRUEVAL, FALSEVAL). If the type of the boolean COND is not
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// i1 then the high bits must conform to getSetCCResultContents.
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// i1 then the high bits must conform to getBooleanContents.
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SELECT,
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// Select with condition operator - This selects between a true value and
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@ -347,7 +347,7 @@ namespace ISD {
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// SetCC operator - This evaluates to a true value iff the condition is
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// true. If the result value type is not i1 then the high bits conform
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// to getSetCCResultContents. The operands to this are the left and right
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// to getBooleanContents. The operands to this are the left and right
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// operands to compare (ops #0, and #1) and the condition code to compare
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// them with (op #2) as a CondCodeSDNode.
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SETCC,
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@ -494,7 +494,7 @@ namespace ISD {
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// BRCOND - Conditional branch. The first operand is the chain, the
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// second is the condition, the third is the block to branch to if the
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// condition is true. If the type of the condition is not i1, then the
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// high bits must conform to getSetCCResultContents.
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// high bits must conform to getBooleanContents.
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BRCOND,
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// BR_CC - Conditional branch. The behavior is like that of SELECT_CC, in
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@ -78,10 +78,10 @@ public:
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Extend // Oversized shift pulls in zeros or sign bits.
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};
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enum SetCCResultValue {
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UndefinedSetCCResult, // SetCC returns a garbage/unknown extend.
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ZeroOrOneSetCCResult, // SetCC returns a zero extended result.
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ZeroOrNegativeOneSetCCResult // SetCC returns a sign extended result.
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enum BooleanContent { // How the target represents true/false values.
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UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
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ZeroOrOneBooleanContent, // All bits zero except for bit 0.
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ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
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};
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enum SchedPreference {
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@ -121,10 +121,12 @@ public:
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/// operations.
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virtual MVT getSetCCResultType(const SDValue &) const;
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/// getSetCCResultContents - For targets without boolean registers, this flag
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/// returns information about the contents of the high-bits in the setcc
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/// result register.
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SetCCResultValue getSetCCResultContents() const { return SetCCResultContents;}
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/// getBooleanContents - For targets without i1 registers, this gives the
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/// nature of the high-bits of boolean values held in types wider than i1.
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/// "Boolean values" are special true/false values produced by nodes like
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/// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
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/// Not to be confused with general values promoted from i1.
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BooleanContent getBooleanContents() const { return BooleanContents;}
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/// getSchedulingPreference - Return target scheduling preference.
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SchedPreference getSchedulingPreference() const {
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@ -812,9 +814,9 @@ protected:
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/// amounts. This type defaults to the pointer type.
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void setShiftAmountType(MVT VT) { ShiftAmountTy = VT; }
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/// setSetCCResultContents - Specify how the target extends the result of a
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/// setcc operation in a register.
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void setSetCCResultContents(SetCCResultValue Ty) { SetCCResultContents = Ty; }
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/// setBooleanContents - Specify how the target extends the result of a
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/// boolean value from i1 to a wider type. See getBooleanContents.
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void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; }
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/// setSchedulingPreference - Specify the target scheduling preference.
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void setSchedulingPreference(SchedPreference Pref) {
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@ -1430,9 +1432,9 @@ private:
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OutOfRangeShiftAmount ShiftAmtHandling;
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/// SetCCResultContents - Information about the contents of the high-bits in
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/// the result of a setcc comparison operation.
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SetCCResultValue SetCCResultContents;
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/// BooleanContents - Information about the contents of the high-bits in
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/// boolean values held in a type wider than i1. See getBooleanContents.
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BooleanContent BooleanContents;
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/// SchedPreferenceInfo - The target scheduling preference: shortest possible
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/// total cycles or lowest register usage.
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@ -5444,7 +5444,7 @@ SDValue DAGCombiner::SimplifySelectCC(SDValue N0, SDValue N1,
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// fold select C, 16, 0 -> shl C, 4
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if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() &&
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TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) {
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TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent) {
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// If the caller doesn't want us to simplify this into a zext of a compare,
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// don't do it.
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@ -698,19 +698,19 @@ SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
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SDValue Cond = GetPromotedInteger(N->getOperand(1)); // Promote condition.
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// Make sure the extra bits coming from type promotion conform to
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// getSetCCResultContents.
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// getBooleanContents.
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unsigned CondBits = Cond.getValueSizeInBits();
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switch (TLI.getSetCCResultContents()) {
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switch (TLI.getBooleanContents()) {
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default:
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assert(false && "Unknown SetCCResultValue!");
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case TargetLowering::UndefinedSetCCResult:
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assert(false && "Unknown BooleanContent!");
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case TargetLowering::UndefinedBooleanContent:
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// The promoted value, which may contain rubbish in the upper bits, is fine.
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break;
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case TargetLowering::ZeroOrOneSetCCResult:
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case TargetLowering::ZeroOrOneBooleanContent:
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if (!DAG.MaskedValueIsZero(Cond,APInt::getHighBitsSet(CondBits,CondBits-1)))
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Cond = DAG.getZeroExtendInReg(Cond, MVT::i1);
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break;
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case TargetLowering::ZeroOrNegativeOneSetCCResult:
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case TargetLowering::ZeroOrNegativeOneBooleanContent:
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if (DAG.ComputeNumSignBits(Cond) != CondBits)
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Cond = DAG.getNode(ISD::SIGN_EXTEND_INREG, Cond.getValueType(), Cond,
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DAG.getValueType(MVT::i1));
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@ -830,27 +830,27 @@ SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
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assert(isTypeLegal(SVT) && "Illegal SetCC type!");
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assert(Cond.getValueType().bitsLE(SVT) && "Unexpected SetCC type!");
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// Make sure the extra bits conform to getSetCCResultContents. There are
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// Make sure the extra bits conform to getBooleanContents. There are
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// two sets of extra bits: those in Cond, which come from type promotion,
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// and those we need to add to have the final type be SVT (for most targets
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// this last set of bits is empty).
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unsigned CondBits = Cond.getValueSizeInBits();
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ISD::NodeType ExtendCode;
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switch (TLI.getSetCCResultContents()) {
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switch (TLI.getBooleanContents()) {
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default:
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assert(false && "Unknown SetCCResultValue!");
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case TargetLowering::UndefinedSetCCResult:
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assert(false && "Unknown BooleanContent!");
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case TargetLowering::UndefinedBooleanContent:
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// Extend to SVT by adding rubbish.
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ExtendCode = ISD::ANY_EXTEND;
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break;
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case TargetLowering::ZeroOrOneSetCCResult:
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case TargetLowering::ZeroOrOneBooleanContent:
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ExtendCode = ISD::ZERO_EXTEND;
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if (!DAG.MaskedValueIsZero(Cond,APInt::getHighBitsSet(CondBits,CondBits-1)))
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// All extra bits need to be cleared. Do this by zero extending the
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// original condition value all the way to SVT.
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Cond = N->getOperand(0);
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break;
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case TargetLowering::ZeroOrNegativeOneSetCCResult: {
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case TargetLowering::ZeroOrNegativeOneBooleanContent: {
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ExtendCode = ISD::SIGN_EXTEND;
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unsigned SignBits = DAG.ComputeNumSignBits(Cond);
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if (SignBits != CondBits)
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@ -210,8 +210,8 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
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if (NVT.bitsLE(SVT)) {
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// The SETCC result type is bigger than the vector element type.
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// Ensure the SETCC result is sign-extended.
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if (TLI.getSetCCResultContents() !=
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TargetLowering::ZeroOrNegativeOneSetCCResult)
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if (TLI.getBooleanContents() !=
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TargetLowering::ZeroOrNegativeOneBooleanContent)
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Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, SVT, Res,
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DAG.getValueType(MVT::i1));
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// Truncate to the final type.
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@ -219,8 +219,8 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
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} else {
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// The SETCC result type is smaller than the vector element type.
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// If the SetCC result is not sign-extended, chop it down to MVT::i1.
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if (TLI.getSetCCResultContents() !=
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TargetLowering::ZeroOrNegativeOneSetCCResult)
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if (TLI.getBooleanContents() !=
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TargetLowering::ZeroOrNegativeOneBooleanContent)
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Res = DAG.getNode(ISD::TRUNCATE, MVT::i1, Res);
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// Sign extend to the final type.
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return DAG.getNode(ISD::SIGN_EXTEND, NVT, Res);
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@ -1495,10 +1495,10 @@ void SelectionDAG::ComputeMaskedBits(SDValue Op, const APInt &Mask,
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case ISD::UADDO:
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if (Op.getResNo() != 1)
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return;
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// The boolean result conforms to getSetCCResultContents. Fall through.
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// The boolean result conforms to getBooleanContents. Fall through.
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case ISD::SETCC:
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// If we know the result of a setcc has the top bits zero, use this info.
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if (TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult &&
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if (TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent &&
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BitWidth > 1)
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KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
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return;
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@ -1903,11 +1903,11 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, unsigned Depth) const{
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case ISD::UADDO:
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if (Op.getResNo() != 1)
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break;
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// The boolean result conforms to getSetCCResultContents. Fall through.
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// The boolean result conforms to getBooleanContents. Fall through.
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case ISD::SETCC:
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// If setcc returns 0/-1, all bits are sign bits.
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if (TLI.getSetCCResultContents() ==
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TargetLowering::ZeroOrNegativeOneSetCCResult)
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if (TLI.getBooleanContents() ==
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TargetLowering::ZeroOrNegativeOneBooleanContent)
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return VTBits;
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break;
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case ISD::ROTL:
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@ -462,7 +462,7 @@ TargetLowering::TargetLowering(TargetMachine &tm)
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StackPointerRegisterToSaveRestore = 0;
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ExceptionPointerRegister = 0;
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ExceptionSelectorRegister = 0;
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SetCCResultContents = UndefinedSetCCResult;
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BooleanContents = UndefinedBooleanContent;
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SchedPreferenceInfo = SchedulingForLatency;
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JumpBufSize = 0;
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JumpBufAlignment = 0;
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@ -41,7 +41,7 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM)
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// Set up the TargetLowering object.
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//I am having problems with shr n ubyte 1
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setShiftAmountType(MVT::i64);
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setSetCCResultContents(ZeroOrOneSetCCResult);
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setBooleanContents(ZeroOrOneBooleanContent);
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setUsesGlobalOffsetTable(true);
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@ -393,7 +393,7 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM)
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setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
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setShiftAmountType(MVT::i32);
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setSetCCResultContents(ZeroOrOneSetCCResult);
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setBooleanContents(ZeroOrOneBooleanContent);
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setStackPointerRegisterToSaveRestore(SPU::R1);
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// Mips does not have i1 type, so use i32 for
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// setcc operations results (slt, sgt, ...).
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setSetCCResultContents(ZeroOrOneSetCCResult);
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setBooleanContents(ZeroOrOneBooleanContent);
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// JumpTable targets must use GOT when using PIC_
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setUsesGlobalOffsetTable(true);
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@ -341,7 +341,7 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
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}
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setShiftAmountType(MVT::i32);
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setSetCCResultContents(ZeroOrOneSetCCResult);
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setBooleanContents(ZeroOrOneBooleanContent);
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if (TM.getSubtarget<PPCSubtarget>().isPPC64()) {
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setStackPointerRegisterToSaveRestore(PPC::X1);
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@ -63,7 +63,7 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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// X86 is weird, it always uses i8 for shift amounts and setcc results.
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setShiftAmountType(MVT::i8);
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setSetCCResultContents(ZeroOrOneSetCCResult);
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setBooleanContents(ZeroOrOneBooleanContent);
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setSchedulingPreference(SchedulingForRegPressure);
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setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0
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setStackPointerRegisterToSaveRestore(X86StackPtr);
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@ -74,7 +74,7 @@ XCoreTargetLowering::XCoreTargetLowering(XCoreTargetMachine &XTM)
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setSchedulingPreference(SchedulingForRegPressure);
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// Use i32 for setcc operations results (slt, sgt, ...).
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setSetCCResultContents(ZeroOrOneSetCCResult);
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setBooleanContents(ZeroOrOneBooleanContent);
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// XCore does not have the NodeTypes below.
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setOperationAction(ISD::BR_CC, MVT::Other, Expand);
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