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More FMA folding opportunities.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225380 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Olivier Sallenave
2015-01-07 20:54:17 +00:00
parent 50bf54ccf4
commit 033a537a84
3 changed files with 305 additions and 1 deletions
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134
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@@ -6878,7 +6878,6 @@ SDValue DAGCombiner::visitFADD(SDNode *N) {
}
} // enable-unsafe-fp-math
// FADD -> FMA combines:
if ((Options.AllowFPOpFusion == FPOpFusion::Fast || Options.UnsafeFPMath) &&
TLI.isFMAFasterThanFMulAndFAdd(VT) &&
@@ -6896,6 +6895,50 @@ SDValue DAGCombiner::visitFADD(SDNode *N) {
(N1->hasOneUse() || TLI.enableAggressiveFMAFusion(VT)))
return DAG.getNode(ISD::FMA, SDLoc(N), VT,
N1.getOperand(0), N1.getOperand(1), N0);
// Remove FP_EXTEND when there is an opportunity to combine. This is
// legal here since extra precision is allowed.
// fold (fadd (fpext (fmul x, y)), z) -> (fma x, y, z)
if (N0.getOpcode() == ISD::FP_EXTEND) {
SDValue N00 = N0.getOperand(0);
if (N00.getOpcode() == ISD::FMUL)
return DAG.getNode(ISD::FMA, SDLoc(N), VT,
N00.getOperand(0), N00.getOperand(1), N1);
}
// fold (fadd x, (fpext (fmul y, z)), z) -> (fma y, z, x)
// Note: Commutes FADD operands.
if (N1.getOpcode() == ISD::FP_EXTEND) {
SDValue N10 = N1.getOperand(0);
if (N10.getOpcode() == ISD::FMUL)
return DAG.getNode(ISD::FMA, SDLoc(N), VT,
N10.getOperand(0), N10.getOperand(1), N0);
}
}
// More folding opportunities when target permits.
if (TLI.enableAggressiveFMAFusion(VT)) {
// fold (fadd (fma x, y, (fmul u, v)), z) -> (fma x, y (fma u, v, z))
if (N0.getOpcode() == ISD::FMA &&
N0.getOperand(2).getOpcode() == ISD::FMUL)
return DAG.getNode(ISD::FMA, SDLoc(N), VT,
N0.getOperand(0), N0.getOperand(1),
DAG.getNode(ISD::FMA, SDLoc(N), VT,
N0.getOperand(2).getOperand(0),
N0.getOperand(2).getOperand(1),
N1));
// fold (fadd x, (fma y, z, (fmul u, v)) -> (fma y, z (fma u, v, x))
if (N1->getOpcode() == ISD::FMA &&
N1.getOperand(2).getOpcode() == ISD::FMUL)
return DAG.getNode(ISD::FMA, SDLoc(N), VT,
N1.getOperand(0), N1.getOperand(1),
DAG.getNode(ISD::FMA, SDLoc(N), VT,
N1.getOperand(2).getOperand(0),
N1.getOperand(2).getOperand(1),
N0));
}
return SDValue();
@@ -6989,6 +7032,95 @@ SDValue DAGCombiner::visitFSUB(SDNode *N) {
DAG.getNode(ISD::FNEG, dl, VT, N00), N01,
DAG.getNode(ISD::FNEG, dl, VT, N1));
}
// Remove FP_EXTEND when there is an opportunity to combine. This is
// legal here since extra precision is allowed.
// fold (fsub (fpext (fmul x, y)), z) -> (fma x, y, (fneg z))
if (N0.getOpcode() == ISD::FP_EXTEND) {
SDValue N00 = N0.getOperand(0);
if (N00.getOpcode() == ISD::FMUL)
return DAG.getNode(ISD::FMA, SDLoc(N), VT,
N00.getOperand(0),
N00.getOperand(1),
DAG.getNode(ISD::FNEG, SDLoc(N), VT, N1));
}
// fold (fsub x, (fpext (fmul y, z))) -> (fma (fneg y), z, x)
// Note: Commutes FSUB operands.
if (N1.getOpcode() == ISD::FP_EXTEND) {
SDValue N10 = N1.getOperand(0);
if (N10.getOpcode() == ISD::FMUL)
return DAG.getNode(ISD::FMA, SDLoc(N), VT,
DAG.getNode(ISD::FNEG, SDLoc(N), VT,
N10.getOperand(0)),
N10.getOperand(1),
N0);
}
// fold (fsub (fpext (fneg (fmul, x, y))), z)
// -> (fma (fneg x), y, (fneg z))
if (N0.getOpcode() == ISD::FP_EXTEND) {
SDValue N00 = N0.getOperand(0);
if (N00.getOpcode() == ISD::FNEG) {
SDValue N000 = N00.getOperand(0);
if (N000.getOpcode() == ISD::FMUL) {
return DAG.getNode(ISD::FMA, dl, VT,
DAG.getNode(ISD::FNEG, dl, VT,
N000.getOperand(0)),
N000.getOperand(1),
DAG.getNode(ISD::FNEG, dl, VT, N1));
}
}
}
// fold (fsub (fneg (fpext (fmul, x, y))), z)
// -> (fma (fneg x), y, (fneg z))
if (N0.getOpcode() == ISD::FNEG) {
SDValue N00 = N0.getOperand(0);
if (N00.getOpcode() == ISD::FP_EXTEND) {
SDValue N000 = N00.getOperand(0);
if (N000.getOpcode() == ISD::FMUL) {
return DAG.getNode(ISD::FMA, dl, VT,
DAG.getNode(ISD::FNEG, dl, VT,
N000.getOperand(0)),
N000.getOperand(1),
DAG.getNode(ISD::FNEG, dl, VT, N1));
}
}
}
// More folding opportunities when target permits.
if (TLI.enableAggressiveFMAFusion(VT)) {
// fold (fsub (fma x, y, (fmul u, v)), z)
// -> (fma x, y (fma u, v, (fneg z)))
if (N0.getOpcode() == ISD::FMA &&
N0.getOperand(2).getOpcode() == ISD::FMUL)
return DAG.getNode(ISD::FMA, SDLoc(N), VT,
N0.getOperand(0), N0.getOperand(1),
DAG.getNode(ISD::FMA, SDLoc(N), VT,
N0.getOperand(2).getOperand(0),
N0.getOperand(2).getOperand(1),
DAG.getNode(ISD::FNEG, SDLoc(N), VT,
N1)));
// fold (fsub x, (fma y, z, (fmul u, v)))
// -> (fma (fneg y), z, (fma (fneg u), v, x))
if (N1.getOpcode() == ISD::FMA &&
N1.getOperand(2).getOpcode() == ISD::FMUL) {
SDValue N20 = N1.getOperand(2).getOperand(0);
SDValue N21 = N1.getOperand(2).getOperand(1);
return DAG.getNode(ISD::FMA, SDLoc(N), VT,
DAG.getNode(ISD::FNEG, SDLoc(N), VT,
N1.getOperand(0)),
N1.getOperand(1),
DAG.getNode(ISD::FMA, SDLoc(N), VT,
DAG.getNode(ISD::FNEG, SDLoc(N), VT,
N20),
N21, N0));
}
}
}
return SDValue();