diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 087737336be..2e82b362e65 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -5366,20 +5366,25 @@ SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
 SDOperand SelectionDAGLegalize::
 ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
   MVT::ValueType SourceVT = Source.getValueType();
-  assert(getTypeAction(SourceVT) == Expand &&
-         "This is not an expansion!");
+  bool ExpandSource = getTypeAction(SourceVT) == Expand;
 
   if (!isSigned) {
     // The integer value loaded will be incorrectly if the 'sign bit' of the
     // incoming integer is set.  To handle this, we dynamically test to see if
     // it is set, and, if so, add a fudge factor.
-    SDOperand Lo, Hi;
-    ExpandOp(Source, Lo, Hi);
+    SDOperand Hi;
+    if (ExpandSource) {
+      SDOperand Lo;
+      ExpandOp(Source, Lo, Hi);
+      Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, Lo, Hi);
+    } else {
+      // The comparison for the sign bit will use the entire operand.
+      Hi = Source;
+    }
 
     // If this is unsigned, and not supported, first perform the conversion to
     // signed, then adjust the result if the sign bit is set.
-    SDOperand SignedConv = ExpandIntToFP(true, DestTy,
-                   DAG.getNode(ISD::BUILD_PAIR, SourceVT, Lo, Hi));
+    SDOperand SignedConv = ExpandIntToFP(true, DestTy, Source);
 
     SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
                                      DAG.getConstant(0, Hi.getValueType()),
@@ -5437,17 +5442,23 @@ ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
 
   // Expand the source, then glue it back together for the call.  We must expand
   // the source in case it is shared (this pass of legalize must traverse it).
-  SDOperand SrcLo, SrcHi;
-  ExpandOp(Source, SrcLo, SrcHi);
-  Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, SrcLo, SrcHi);
+  if (ExpandSource) {
+    SDOperand SrcLo, SrcHi;
+    ExpandOp(Source, SrcLo, SrcHi);
+    Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, SrcLo, SrcHi);
+  }
 
   RTLIB::Libcall LC;
   if (SourceVT == MVT::i64) {
     if (DestTy == MVT::f32)
       LC = RTLIB::SINTTOFP_I64_F32;
-    else {
-      assert(DestTy == MVT::f64 && "Unknown fp value type!");
+    else if (DestTy == MVT::f64)
       LC = RTLIB::SINTTOFP_I64_F64;
+    else if (DestTy == MVT::f80)
+      LC = RTLIB::SINTTOFP_I64_F80;
+    else {
+      assert(DestTy == MVT::ppcf128 && "Unknown fp value type!");
+      LC = RTLIB::SINTTOFP_I64_PPCF128;
     }
   } else if (SourceVT == MVT::i128) {
     if (DestTy == MVT::f32)
diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index 32787bcc75b..a224b036926 100644
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -2380,6 +2380,10 @@ SDOperand PPCTargetLowering::LowerFP_ROUND_INREG(SDOperand Op,
 }
 
 SDOperand PPCTargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
+  // Don't handle ppc_fp128 here; let it be lowered to a libcall.
+  if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
+    return SDOperand();
+
   if (Op.getOperand(0).getValueType() == MVT::i64) {
     SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0));
     SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits);
diff --git a/test/CodeGen/PowerPC/int-fp-conv.ll b/test/CodeGen/PowerPC/int-fp-conv-0.ll
similarity index 100%
rename from test/CodeGen/PowerPC/int-fp-conv.ll
rename to test/CodeGen/PowerPC/int-fp-conv-0.ll
diff --git a/test/CodeGen/PowerPC/int-fp-conv-1.ll b/test/CodeGen/PowerPC/int-fp-conv-1.ll
new file mode 100644
index 00000000000..3d6667539f2
--- /dev/null
+++ b/test/CodeGen/PowerPC/int-fp-conv-1.ll
@@ -0,0 +1,11 @@
+; RUN: llvm-as < %s | llc -march=ppc64 | grep __floatditf
+
+define i64 @__fixunstfdi(ppc_fp128 %a) nounwind  {
+entry:
+	%tmp1213 = uitofp i64 0 to ppc_fp128		; <ppc_fp128> [#uses=1]
+	%tmp15 = sub ppc_fp128 %a, %tmp1213		; <ppc_fp128> [#uses=1]
+	%tmp2829 = fptoui ppc_fp128 %tmp15 to i32		; <i32> [#uses=1]
+	%tmp282930 = zext i32 %tmp2829 to i64		; <i64> [#uses=1]
+	%tmp32 = add i64 %tmp282930, 0		; <i64> [#uses=1]
+	ret i64 %tmp32
+}