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fix load bug
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20061 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -624,18 +624,17 @@ unsigned ISel::SelectExpr(SDOperand N) {
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SDOperand Address = N.getOperand(1);
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Select(Chain);
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switch(Node->getValueType(0)) {
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default: Node->dump(); assert(0 && "Unknown type to sign extend to.");
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case MVT::i64:
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assert(Node->getValueType(0) == MVT::i64 && "Unknown type to sign extend to.");
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if (opcode == ISD::LOAD)
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Opc = Alpha::LDQ;
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else
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switch (cast<MVTSDNode>(Node)->getExtraValueType()) {
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default: Node->dump(); assert(0 && "Bad sign extend!");
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case MVT::i64: Opc = Alpha::LDQ; assert(opcode == ISD::LOAD && "Not Load"); break;
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case MVT::i32: Opc = Alpha::LDL; assert(opcode != ISD::ZEXTLOAD && "Not sext"); break;
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case MVT::i16: Opc = Alpha::LDWU; assert(opcode != ISD::SEXTLOAD && "Not zext"); break;
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case MVT::i1: //FIXME: Treat i1 as i8 since there are problems otherwise
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case MVT::i8: Opc = Alpha::LDBU; assert(opcode != ISD::SEXTLOAD && "Not zext"); break;
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}
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}
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if (Address.getOpcode() == ISD::GlobalAddress)
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{
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@ -1106,6 +1105,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
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{
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assert (DestType == MVT::i64 && "only quads can be loaded to");
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MVT::ValueType SrcType = N.getOperand(0).getValueType();
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assert (SrcType == MVT::f32 || SrcType == MVT::f64);
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Tmp1 = SelectExpr(N.getOperand(0)); // Get the operand register
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//The hard way:
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