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ARM assembly parsing and encoding for LDR instructions.
Enhance support for LDR instruction assembly parsing for post-indexed addressing with immediate values. Add tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136940 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -673,11 +673,15 @@ def am2offset_reg : Operand<i32>,
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let MIOperandInfo = (ops GPR, i32imm);
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}
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// FIXME: am2offset_imm should only need the immediate, not the GPR. Having
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// the GPR is purely vestigal at this point.
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def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; }
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def am2offset_imm : Operand<i32>,
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ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm",
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[], [SDNPWantRoot]> {
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let EncoderMethod = "getAddrMode2OffsetOpValue";
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let PrintMethod = "printAddrMode2OffsetOperand";
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let ParserMatchClass = AM2OffsetImmAsmOperand;
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let MIOperandInfo = (ops GPR, i32imm);
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}
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@ -1910,31 +1914,33 @@ multiclass AI2_ldridx<bit isByte, string opc, InstrItinClass itin> {
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}
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def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
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(ins GPR:$Rn, am2offset_reg:$offset),
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(ins addr_offset_none:$addr, am2offset_reg:$offset),
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IndexModePost, LdFrm, itin,
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opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
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opc, "\t$Rt, $addr, $offset",
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"$addr.base = $Rn_wb", []> {
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// {12} isAdd
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// {11-0} imm12/Rm
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bits<14> offset;
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bits<4> Rn;
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bits<4> addr;
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let Inst{25} = 1;
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let Inst{23} = offset{12};
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let Inst{19-16} = Rn;
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let Inst{19-16} = addr;
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let Inst{11-0} = offset{11-0};
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let DecoderMethod = "DecodeAddrMode2IdxInstruction";
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}
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def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
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(ins GPR:$Rn, am2offset_imm:$offset),
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(ins addr_offset_none:$addr, am2offset_imm:$offset),
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IndexModePost, LdFrm, itin,
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opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
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opc, "\t$Rt, $addr, $offset",
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"$addr.base = $Rn_wb", []> {
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// {12} isAdd
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// {11-0} imm12/Rm
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bits<14> offset;
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bits<4> Rn;
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bits<4> addr;
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let Inst{25} = 0;
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let Inst{23} = offset{12};
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let Inst{19-16} = Rn;
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let Inst{19-16} = addr;
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let Inst{11-0} = offset{11-0};
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let DecoderMethod = "DecodeAddrMode2IdxInstruction";
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}
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@ -520,6 +520,15 @@ public:
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int64_t Val = Mem.OffsetImm->getValue();
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return Val > -4096 && Val < 4096;
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}
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bool isAM2OffsetImm() const {
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if (Kind != Immediate)
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return false;
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// Immediate offset in range [-4095, 4095].
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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if (!CE) return false;
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int64_t Val = CE->getValue();
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return Val > -4096 && Val < 4096;
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}
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bool isAddrMode5() const {
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if (Kind != Memory)
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return false;
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@ -780,6 +789,20 @@ public:
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Inst.addOperand(MCOperand::CreateImm(Val));
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}
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void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
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assert(N == 2 && "Invalid number of operands!");
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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assert(CE && "non-constant AM2OffsetImm operand!");
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int32_t Val = CE->getValue();
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ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
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// Special case for #-0
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if (Val == INT32_MIN) Val = 0;
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if (Val < 0) Val = -Val;
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Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
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Inst.addOperand(MCOperand::CreateReg(0));
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Inst.addOperand(MCOperand::CreateImm(Val));
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}
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void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
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assert(N == 2 && "Invalid number of operands!");
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// The lower two bits are always zero and as such are not encoded.
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