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Change conditional instructions definitions, e.g. ANDCC, ARMPseudoExpand and t2PseudoExpand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153135 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
7edc277f72
commit
03a1852538
@ -4085,74 +4085,43 @@ def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
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[/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
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RegConstraint<"$false = $Rd">;
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let isCodeGenOnly = 1 in {
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// Conditional instructions
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multiclass AsI1_bincc_irs<bits<4> opcod, string opc,
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InstrItinClass iii, InstrItinClass iir, InstrItinClass iis> {
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def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
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iii, opc, "\t$Rd, $Rn, $imm", []>,
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RegConstraint<"$Rn = $Rd"> {
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bits<4> Rd;
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bits<4> Rn;
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bits<12> imm;
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let Inst{25} = 1;
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let Inst{19-16} = Rn;
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let Inst{15-12} = Rd;
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let Inst{11-0} = imm;
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}
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def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
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iir, opc, "\t$Rd, $Rn, $Rm", []>,
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RegConstraint<"$Rn = $Rd"> {
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bits<4> Rd;
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bits<4> Rn;
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bits<4> Rm;
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let Inst{25} = 0;
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let Inst{19-16} = Rn;
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let Inst{15-12} = Rd;
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let Inst{11-4} = 0b00000000;
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let Inst{3-0} = Rm;
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}
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multiclass AsI1_bincc_irs<Instruction iri, Instruction irr, Instruction irsi,
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Instruction irsr,
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InstrItinClass iii, InstrItinClass iir,
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InstrItinClass iis> {
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def ri : ARMPseudoExpand<(outs GPR:$Rd),
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(ins GPR:$Rn, so_imm:$imm, pred:$p, cc_out:$s),
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4, iii, [],
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(iri GPR:$Rd, GPR:$Rn, so_imm:$imm, pred:$p, cc_out:$s)>,
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RegConstraint<"$Rn = $Rd">;
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def rr : ARMPseudoExpand<(outs GPR:$Rd),
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(ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
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4, iir, [],
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(irr GPR:$Rd, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
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RegConstraint<"$Rn = $Rd">;
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def rsi : ARMPseudoExpand<(outs GPR:$Rd),
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(ins GPR:$Rn, so_reg_imm:$shift, pred:$p, cc_out:$s),
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4, iis, [],
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(irsi GPR:$Rd, GPR:$Rn, so_reg_imm:$shift, pred:$p, cc_out:$s)>,
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RegConstraint<"$Rn = $Rd">;
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def rsr : ARMPseudoExpand<(outs GPRnopc:$Rd),
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(ins GPRnopc:$Rn, so_reg_reg:$shift, pred:$p, cc_out:$s),
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4, iis, [],
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(irsr GPR:$Rd, GPR:$Rn, so_reg_reg:$shift, pred:$p, cc_out:$s)>,
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RegConstraint<"$Rn = $Rd">;
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}
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def rsi : AsI1<opcod, (outs GPR:$Rd),
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(ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
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iis, opc, "\t$Rd, $Rn, $shift", []>,
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RegConstraint<"$Rn = $Rd"> {
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bits<4> Rd;
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bits<4> Rn;
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bits<12> shift;
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let Inst{25} = 0;
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let Inst{19-16} = Rn;
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let Inst{15-12} = Rd;
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let Inst{11-5} = shift{11-5};
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let Inst{4} = 0;
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let Inst{3-0} = shift{3-0};
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}
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defm ANDCC : AsI1_bincc_irs<ANDri, ANDrr, ANDrsi, ANDrsr,
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IIC_iBITi, IIC_iBITr, IIC_iBITsr>;
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defm ORRCC : AsI1_bincc_irs<ORRri, ORRrr, ORRrsi, ORRrsr,
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IIC_iBITi, IIC_iBITr, IIC_iBITsr>;
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defm EORCC : AsI1_bincc_irs<EORri, EORrr, EORrsi, EORrsr,
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IIC_iBITi, IIC_iBITr, IIC_iBITsr>;
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def rsr : AsI1<opcod, (outs GPRnopc:$Rd),
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(ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
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iis, opc, "\t$Rd, $Rn, $shift", []>,
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RegConstraint<"$Rn = $Rd"> {
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bits<4> Rd;
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bits<4> Rn;
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bits<12> shift;
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let Inst{25} = 0;
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let Inst{19-16} = Rn;
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let Inst{15-12} = Rd;
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let Inst{11-8} = shift{11-8};
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let Inst{7} = 0;
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let Inst{6-5} = shift{6-5};
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let Inst{4} = 1;
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let Inst{3-0} = shift{3-0};
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}
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} // AsI1_bincc_irs
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defm ANDCC : AsI1_bincc_irs<0b0000, "and", IIC_iBITi, IIC_iBITr, IIC_iBITsr>;
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defm ORRCC : AsI1_bincc_irs<0b1100, "orr", IIC_iBITi, IIC_iBITr, IIC_iBITsr>;
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defm EORCC : AsI1_bincc_irs<0b0001, "eor", IIC_iBITi, IIC_iBITr, IIC_iBITsr>;
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} // isCodeGenOnly
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} // neverHasSideEffects
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//===----------------------------------------------------------------------===//
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// Atomic operations intrinsics
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//
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@ -2952,45 +2952,36 @@ def t2MOVCCror : T2I_movcc_sh<0b11, (outs rGPR:$Rd),
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(ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
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IIC_iCMOVsi, "ror", ".w\t$Rd, $Rm, $imm", []>,
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RegConstraint<"$false = $Rd">;
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} // isCodeGenOnly = 1
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multiclass T2I_bincc_irs<bits<4> opcod, string opc,
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multiclass T2I_bincc_irs<Instruction iri, Instruction irr, Instruction irs,
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InstrItinClass iii, InstrItinClass iir, InstrItinClass iis> {
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// shifted imm
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def ri : T2sTwoRegImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm),
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iii, opc, ".w\t$Rd, $Rn, $imm", []>,
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RegConstraint<"$Rn = $Rd"> {
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let Inst{31-27} = 0b11110;
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let Inst{25} = 0;
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let Inst{24-21} = opcod;
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let Inst{15} = 0;
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}
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def ri : t2PseudoExpand<(outs rGPR:$Rd),
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(ins rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s),
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4, iii, [],
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(iri rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>,
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RegConstraint<"$Rn = $Rd">;
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// register
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def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
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iir, opc, ".w\t$Rd, $Rn, $Rm", []>,
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RegConstraint<"$Rn = $Rd"> {
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let Inst{31-27} = 0b11101;
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let Inst{26-25} = 0b01;
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let Inst{24-21} = opcod;
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let Inst{14-12} = 0b000; // imm3
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let Inst{7-6} = 0b00; // imm2
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let Inst{5-4} = 0b00; // type
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}
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def rr : t2PseudoExpand<(outs rGPR:$Rd),
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(ins rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s),
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4, iir, [],
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(irr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>,
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RegConstraint<"$Rn = $Rd">;
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// shifted register
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def rs : T2sTwoRegShiftedReg<(outs rGPR:$Rd),
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(ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
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iis, opc, ".w\t$Rd, $Rn, $ShiftedRm", []>,
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RegConstraint<"$Rn = $Rd"> {
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let Inst{31-27} = 0b11101;
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let Inst{26-25} = 0b01;
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let Inst{24-21} = opcod;
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}
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def rs : t2PseudoExpand<(outs rGPR:$Rd),
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(ins rGPR:$Rn, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s),
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4, iis, [],
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(irs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s)>,
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RegConstraint<"$Rn = $Rd">;
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} // T2I_bincc_irs
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defm t2ANDCC : T2I_bincc_irs<0b0000, "and", IIC_iBITi, IIC_iBITr, IIC_iBITsi>;
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defm t2ORRCC : T2I_bincc_irs<0b0010, "orr", IIC_iBITi, IIC_iBITr, IIC_iBITsi>;
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defm t2EORCC : T2I_bincc_irs<0b0100, "eor", IIC_iBITi, IIC_iBITr, IIC_iBITsi>;
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} // isCodeGenOnly = 1
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defm t2ANDCC : T2I_bincc_irs<t2ANDri, t2ANDrr, t2ANDrs,
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IIC_iBITi, IIC_iBITr, IIC_iBITsi>;
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defm t2ORRCC : T2I_bincc_irs<t2ORRri, t2ORRrr, t2ORRrs,
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IIC_iBITi, IIC_iBITr, IIC_iBITsi>;
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defm t2EORCC : T2I_bincc_irs<t2EORri, t2EORrr, t2EORrs,
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IIC_iBITi, IIC_iBITr, IIC_iBITsi>;
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} // neverHasSideEffects
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//===----------------------------------------------------------------------===//
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