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Extend r148086 to check for [r +/- reg] address mode. This fixes queens performance regression (due to increased register pressure from overly aggressive pre-inc formation).

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152162 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2012-03-06 23:33:32 +00:00
parent 4d0983a4d7
commit 03be3622aa
2 changed files with 15 additions and 8 deletions
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12
test/CodeGen/ARM/shifter_operand.ll
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@@ -54,12 +54,16 @@ declare i8* @malloc(...)
define fastcc void @test4(i16 %addr) nounwind {
entry:
; A8: test4:
; A8: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]!
; A8: str [[REG]], [r0]
; A8: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]
; A8-NOT: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]!
; A8: str [[REG]], [r0, r1, lsl #2]
; A8-NOT: str [[REG]], [r0]
; A9: test4:
; A9: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]!
; A9: str [[REG]], [r0]
; A9: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]
; A9-NOT: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]!
; A9: str [[REG]], [r0, r1, lsl #2]
; A9-NOT: str [[REG]], [r0]
%0 = tail call i8* (...)* @malloc(i32 undef) nounwind
%1 = bitcast i8* %0 to i32*
%2 = sext i16 %addr to i32