From 03c735b42cd4857213e4c1e2caeae9c460e8d0d4 Mon Sep 17 00:00:00 2001 From: Reid Kleckner Date: Mon, 1 Dec 2014 21:04:44 +0000 Subject: [PATCH] Parse 'ghccc' in .ll files as the GHC convention (cc 10) Previously we just used "cc 10" in the .ll files, but that isn't very human readable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223076 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/AsmParser/LLLexer.cpp | 1 + lib/AsmParser/LLParser.cpp | 4 +++- lib/AsmParser/LLToken.h | 1 + lib/IR/AsmWriter.cpp | 1 + test/Bitcode/calling-conventions.3.2.ll | 4 ++-- test/CodeGen/ARM/ghc-tcreturn-lowered.ll | 10 +++++----- test/CodeGen/X86/ghc-cc.ll | 10 +++++----- test/CodeGen/X86/ghc-cc64.ll | 10 +++++----- test/CodeGen/X86/sibcall-4.ll | 4 ++-- test/CodeGen/X86/tailcall-returndup-void.ll | 10 +++++----- test/Feature/callingconventions.ll | 7 +++++++ .../DeadStoreElimination/2011-03-25-DSEMiscompile.ll | 6 +++--- 12 files changed, 40 insertions(+), 28 deletions(-) diff --git a/lib/AsmParser/LLLexer.cpp b/lib/AsmParser/LLLexer.cpp index 6523bcee060..07c13b7ecab 100644 --- a/lib/AsmParser/LLLexer.cpp +++ b/lib/AsmParser/LLLexer.cpp @@ -596,6 +596,7 @@ lltok::Kind LLLexer::LexIdentifier() { KEYWORD(anyregcc); KEYWORD(preserve_mostcc); KEYWORD(preserve_allcc); + KEYWORD(ghccc); KEYWORD(cc); KEYWORD(c); diff --git a/lib/AsmParser/LLParser.cpp b/lib/AsmParser/LLParser.cpp index 2c835f9975b..4a4cc95975d 100644 --- a/lib/AsmParser/LLParser.cpp +++ b/lib/AsmParser/LLParser.cpp @@ -1443,7 +1443,7 @@ bool LLParser::ParseOptionalDLLStorageClass(unsigned &Res) { /// ::= /*empty*/ /// ::= 'ccc' /// ::= 'fastcc' -/// ::= 'kw_intel_ocl_bicc' +/// ::= 'intel_ocl_bicc' /// ::= 'coldcc' /// ::= 'x86_stdcallcc' /// ::= 'x86_fastcallcc' @@ -1463,6 +1463,7 @@ bool LLParser::ParseOptionalDLLStorageClass(unsigned &Res) { /// ::= 'anyregcc' /// ::= 'preserve_mostcc' /// ::= 'preserve_allcc' +/// ::= 'ghccc' /// ::= 'cc' UINT /// bool LLParser::ParseOptionalCallingConv(unsigned &CC) { @@ -1490,6 +1491,7 @@ bool LLParser::ParseOptionalCallingConv(unsigned &CC) { case lltok::kw_anyregcc: CC = CallingConv::AnyReg; break; case lltok::kw_preserve_mostcc:CC = CallingConv::PreserveMost; break; case lltok::kw_preserve_allcc: CC = CallingConv::PreserveAll; break; + case lltok::kw_ghccc: CC = CallingConv::GHC; break; case lltok::kw_cc: { Lex.Lex(); return ParseUInt32(CC); diff --git a/lib/AsmParser/LLToken.h b/lib/AsmParser/LLToken.h index f9821f76efe..d8583bd2d40 100644 --- a/lib/AsmParser/LLToken.h +++ b/lib/AsmParser/LLToken.h @@ -95,6 +95,7 @@ namespace lltok { kw_x86_64_sysvcc, kw_x86_64_win64cc, kw_webkit_jscc, kw_anyregcc, kw_preserve_mostcc, kw_preserve_allcc, + kw_ghccc, // Attributes: kw_attributes, diff --git a/lib/IR/AsmWriter.cpp b/lib/IR/AsmWriter.cpp index 1961a20901e..e461187a0c6 100644 --- a/lib/IR/AsmWriter.cpp +++ b/lib/IR/AsmWriter.cpp @@ -282,6 +282,7 @@ static void PrintCallingConv(unsigned cc, raw_ostream &Out) { case CallingConv::AnyReg: Out << "anyregcc"; break; case CallingConv::PreserveMost: Out << "preserve_mostcc"; break; case CallingConv::PreserveAll: Out << "preserve_allcc"; break; + case CallingConv::GHC: Out << "ghccc"; break; case CallingConv::X86_StdCall: Out << "x86_stdcallcc"; break; case CallingConv::X86_FastCall: Out << "x86_fastcallcc"; break; case CallingConv::X86_ThisCall: Out << "x86_thiscallcc"; break; diff --git a/test/Bitcode/calling-conventions.3.2.ll b/test/Bitcode/calling-conventions.3.2.ll index f36e9f82a2d..b60f1d70ca0 100644 --- a/test/Bitcode/calling-conventions.3.2.ll +++ b/test/Bitcode/calling-conventions.3.2.ll @@ -15,7 +15,7 @@ declare coldcc void @coldcc() ; CHECK: declare coldcc void @coldcc declare cc10 void @cc10() -; CHECK: declare cc10 void @cc10 +; CHECK: declare ghccc void @cc10 declare spir_kernel void @spir_kernel() ; CHECK: declare spir_kernel void @spir_kernel @@ -72,7 +72,7 @@ define void @call_coldcc() { } define void @call_cc10 () { -; CHECK: call cc10 void @cc10 +; CHECK: call ghccc void @cc10 call cc10 void @cc10 () ret void } diff --git a/test/CodeGen/ARM/ghc-tcreturn-lowered.ll b/test/CodeGen/ARM/ghc-tcreturn-lowered.ll index 6d2564ba1ab..623b4220c21 100644 --- a/test/CodeGen/ARM/ghc-tcreturn-lowered.ll +++ b/test/CodeGen/ARM/ghc-tcreturn-lowered.ll @@ -1,21 +1,21 @@ ; RUN: llc -mtriple=thumbv7-eabi -o - %s | FileCheck %s -declare cc 10 void @g() +declare ghccc void @g() -define cc 10 void @test_direct_tail() { +define ghccc void @test_direct_tail() { ; CHECK-LABEL: test_direct_tail: ; CHECK: b g - tail call cc10 void @g() + tail call ghccc void @g() ret void } @ind_func = global void()* zeroinitializer -define cc 10 void @test_indirect_tail() { +define ghccc void @test_indirect_tail() { ; CHECK-LABEL: test_indirect_tail: ; CHECK: bx {{r[0-9]+}} %func = load void()** @ind_func - tail call cc10 void()* %func() + tail call ghccc void()* %func() ret void } diff --git a/test/CodeGen/X86/ghc-cc.ll b/test/CodeGen/X86/ghc-cc.ll index 4dba2c08632..3ada8c8ce98 100644 --- a/test/CodeGen/X86/ghc-cc.ll +++ b/test/CodeGen/X86/ghc-cc.ll @@ -12,13 +12,13 @@ entry: ; CHECK: movl {{[0-9]*}}(%esp), %ebx ; CHECK-NEXT: movl {{[0-9]*}}(%esp), %ebp ; CHECK-NEXT: calll addtwo - %0 = call cc 10 i32 @addtwo(i32 %a, i32 %b) + %0 = call ghccc i32 @addtwo(i32 %a, i32 %b) ; CHECK: calll foo call void @foo() nounwind ret void } -define cc 10 i32 @addtwo(i32 %x, i32 %y) nounwind { +define ghccc i32 @addtwo(i32 %x, i32 %y) nounwind { entry: ; CHECK: leal (%ebx,%ebp), %eax %0 = add i32 %x, %y @@ -26,7 +26,7 @@ entry: ret i32 %0 } -define cc 10 void @foo() nounwind { +define ghccc void @foo() nounwind { entry: ; CHECK: movl r1, %esi ; CHECK-NEXT: movl hp, %edi @@ -37,8 +37,8 @@ entry: %2 = load i32* @sp %3 = load i32* @base ; CHECK: jmp bar - tail call cc 10 void @bar( i32 %3, i32 %2, i32 %1, i32 %0 ) nounwind + tail call ghccc void @bar( i32 %3, i32 %2, i32 %1, i32 %0 ) nounwind ret void } -declare cc 10 void @bar(i32, i32, i32, i32) +declare ghccc void @bar(i32, i32, i32, i32) diff --git a/test/CodeGen/X86/ghc-cc64.ll b/test/CodeGen/X86/ghc-cc64.ll index 403391e8165..7251dd673b3 100644 --- a/test/CodeGen/X86/ghc-cc64.ll +++ b/test/CodeGen/X86/ghc-cc64.ll @@ -25,13 +25,13 @@ entry: ; CHECK: movq %rdi, %r13 ; CHECK-NEXT: movq %rsi, %rbp ; CHECK-NEXT: callq addtwo - %0 = call cc 10 i64 @addtwo(i64 %a, i64 %b) + %0 = call ghccc i64 @addtwo(i64 %a, i64 %b) ; CHECK: callq foo call void @foo() nounwind ret void } -define cc 10 i64 @addtwo(i64 %x, i64 %y) nounwind { +define ghccc i64 @addtwo(i64 %x, i64 %y) nounwind { entry: ; CHECK: leaq (%r13,%rbp), %rax %0 = add i64 %x, %y @@ -39,7 +39,7 @@ entry: ret i64 %0 } -define cc 10 void @foo() nounwind { +define ghccc void @foo() nounwind { entry: ; CHECK: movsd d2(%rip), %xmm6 ; CHECK-NEXT: movsd d1(%rip), %xmm5 @@ -74,12 +74,12 @@ entry: %14 = load i64* @sp %15 = load i64* @base ; CHECK: jmp bar - tail call cc 10 void @bar( i64 %15, i64 %14, i64 %13, i64 %12, i64 %11, + tail call ghccc void @bar( i64 %15, i64 %14, i64 %13, i64 %12, i64 %11, i64 %10, i64 %9, i64 %8, i64 %7, i64 %6, float %5, float %4, float %3, float %2, double %1, double %0 ) nounwind ret void } -declare cc 10 void @bar(i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, +declare ghccc void @bar(i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, float, float, float, float, double, double) diff --git a/test/CodeGen/X86/sibcall-4.ll b/test/CodeGen/X86/sibcall-4.ll index 980b0f797ee..2c7f51d2802 100644 --- a/test/CodeGen/X86/sibcall-4.ll +++ b/test/CodeGen/X86/sibcall-4.ll @@ -1,13 +1,13 @@ ; RUN: llc < %s -mtriple=i386-pc-linux-gnu | FileCheck %s ; pr7610 -define cc10 void @t(i32* %Base_Arg, i32* %Sp_Arg, i32* %Hp_Arg, i32 %R1_Arg) nounwind { +define ghccc void @t(i32* %Base_Arg, i32* %Sp_Arg, i32* %Hp_Arg, i32 %R1_Arg) nounwind { cm1: ; CHECK-LABEL: t: ; CHECK: jmpl *%eax %nm3 = getelementptr i32* %Sp_Arg, i32 1 %nm9 = load i32* %Sp_Arg %nma = inttoptr i32 %nm9 to void (i32*, i32*, i32*, i32)* - tail call cc10 void %nma(i32* %Base_Arg, i32* %nm3, i32* %Hp_Arg, i32 %R1_Arg) nounwind + tail call ghccc void %nma(i32* %Base_Arg, i32* %nm3, i32* %Hp_Arg, i32 %R1_Arg) nounwind ret void } diff --git a/test/CodeGen/X86/tailcall-returndup-void.ll b/test/CodeGen/X86/tailcall-returndup-void.ll index c1d631225ec..2c39cb4468d 100644 --- a/test/CodeGen/X86/tailcall-returndup-void.ll +++ b/test/CodeGen/X86/tailcall-returndup-void.ll @@ -3,9 +3,9 @@ ; CHECK-NOT: ret @sES_closure = external global [0 x i64] -declare cc10 void @sEH_info(i64* noalias nocapture, i64* noalias nocapture, i64* noalias nocapture, i64, i64, i64) align 8 +declare ghccc void @sEH_info(i64* noalias nocapture, i64* noalias nocapture, i64* noalias nocapture, i64, i64, i64) align 8 -define cc10 void @rBM_info(i64* noalias nocapture %Base_Arg, i64* noalias nocapture %Sp_Arg, i64* noalias nocapture %Hp_Arg, i64 %R1_Arg, i64 %R2_Arg, i64 %R3_Arg) nounwind align 8 { +define ghccc void @rBM_info(i64* noalias nocapture %Base_Arg, i64* noalias nocapture %Sp_Arg, i64* noalias nocapture %Hp_Arg, i64 %R1_Arg, i64 %R2_Arg, i64 %R3_Arg) nounwind align 8 { c263: %ln265 = getelementptr inbounds i64* %Sp_Arg, i64 -2 %ln266 = ptrtoint i64* %ln265 to i64 @@ -18,11 +18,11 @@ n26p: ; preds = %c263 n1ZQ.i: ; preds = %n26p %ln1ZT.i = load i64* getelementptr inbounds ([0 x i64]* @sES_closure, i64 0, i64 0), align 8 %ln1ZU.i = inttoptr i64 %ln1ZT.i to void (i64*, i64*, i64*, i64, i64, i64)* - tail call cc10 void %ln1ZU.i(i64* %Base_Arg, i64* %Sp_Arg, i64* %Hp_Arg, i64 ptrtoint ([0 x i64]* @sES_closure to i64), i64 ptrtoint ([0 x i64]* @sES_closure to i64), i64 %R3_Arg) nounwind + tail call ghccc void %ln1ZU.i(i64* %Base_Arg, i64* %Sp_Arg, i64* %Hp_Arg, i64 ptrtoint ([0 x i64]* @sES_closure to i64), i64 ptrtoint ([0 x i64]* @sES_closure to i64), i64 %R3_Arg) nounwind br label %rBL_info.exit c1ZP.i: ; preds = %n26p - tail call cc10 void @sEH_info(i64* %Base_Arg, i64* %Sp_Arg, i64* %Hp_Arg, i64 ptrtoint ([0 x i64]* @sES_closure to i64), i64 ptrtoint ([0 x i64]* @sES_closure to i64), i64 %R3_Arg) nounwind + tail call ghccc void @sEH_info(i64* %Base_Arg, i64* %Sp_Arg, i64* %Hp_Arg, i64 ptrtoint ([0 x i64]* @sES_closure to i64), i64 ptrtoint ([0 x i64]* @sES_closure to i64), i64 %R3_Arg) nounwind br label %rBL_info.exit rBL_info.exit: ; preds = %c1ZP.i, %n1ZQ.i @@ -32,6 +32,6 @@ c26a: ; preds = %c263 %ln27h = getelementptr inbounds i64* %Base_Arg, i64 -2 %ln27j = load i64* %ln27h, align 8 %ln27k = inttoptr i64 %ln27j to void (i64*, i64*, i64*, i64, i64, i64)* - tail call cc10 void %ln27k(i64* %Base_Arg, i64* %Sp_Arg, i64* %Hp_Arg, i64 %R1_Arg, i64 %R2_Arg, i64 %R3_Arg) nounwind + tail call ghccc void %ln27k(i64* %Base_Arg, i64* %Sp_Arg, i64* %Hp_Arg, i64 %R1_Arg, i64 %R2_Arg, i64 %R3_Arg) nounwind ret void } diff --git a/test/Feature/callingconventions.ll b/test/Feature/callingconventions.ll index 192f07a413b..8b339d43fcd 100644 --- a/test/Feature/callingconventions.ll +++ b/test/Feature/callingconventions.ll @@ -52,4 +52,11 @@ U: resume { i8*, i32 } %exn } +declare ghccc void @ghc_callee() + +define void @ghc_caller() { + call ghccc void @ghc_callee() + ret void +} + declare i32 @__gxx_personality_v0(...) diff --git a/test/Transforms/DeadStoreElimination/2011-03-25-DSEMiscompile.ll b/test/Transforms/DeadStoreElimination/2011-03-25-DSEMiscompile.ll index 079eec43bf8..39d53584dc3 100644 --- a/test/Transforms/DeadStoreElimination/2011-03-25-DSEMiscompile.ll +++ b/test/Transforms/DeadStoreElimination/2011-03-25-DSEMiscompile.ll @@ -5,9 +5,9 @@ target triple = "i386-apple-darwin9.8" @A = external global [0 x i32] -declare cc10 void @Func2(i32*, i32*, i32*, i32) +declare ghccc void @Func2(i32*, i32*, i32*, i32) -define cc10 void @Func1(i32* noalias %Arg1, i32* noalias %Arg2, i32* %Arg3, i32 %Arg4) { +define ghccc void @Func1(i32* noalias %Arg1, i32* noalias %Arg2, i32* %Arg3, i32 %Arg4) { entry: store i32 add (i32 ptrtoint ([0 x i32]* @A to i32), i32 1), i32* %Arg2 ; CHECK: store i32 add (i32 ptrtoint ([0 x i32]* @A to i32), i32 1), i32* %Arg2 @@ -18,6 +18,6 @@ entry: %ln2gE = bitcast i32* %ln2gD to double* store double %ln2gB, double* %ln2gE ; CHECK: store double %ln2gB, double* %ln2gE - tail call cc10 void @Func2(i32* %Arg1, i32* %Arg2, i32* %Arg3, i32 %Arg4) nounwind + tail call ghccc void @Func2(i32* %Arg1, i32* %Arg2, i32* %Arg3, i32 %Arg4) nounwind ret void }