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- When performing pre-/post- indexed load/store transformation, do not worry
about whether the new base ptr would be live below the load/store. Let two address pass split it back to non-indexed ops. - Minor tweaks / fixes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31544 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -208,61 +208,26 @@ namespace {
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// Try turning it into a pre-indexed load / store except when
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// 1) Another use of base ptr is a predecessor of N. If ptr is folded
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// that would create a cycle.
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// 2) All uses are load / store ops that use it as base ptr and offset
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// is just an addressing mode immediate.
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// 3) If the would-be new base may not to be dead at N.
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bool OffIsAMImm = Offset.getOpcode() == ISD::Constant && TLI.
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isLegalAddressImmediate(cast<ConstantSDNode>(Offset)->getValue());
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// Check for #3.
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for (SDNode::use_iterator I = BasePtr.Val->use_begin(),
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E = BasePtr.Val->use_end(); I != E; ++I) {
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SDNode *Use = *I;
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if (Use == Ptr.Val)
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continue;
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if (Use->getOpcode() == ISD::CopyToReg)
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return false;
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if (OffIsAMImm && (Use->getOpcode() == ISD::ADD ||
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Use->getOpcode() == ISD::SUB)) {
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for (SDNode::use_iterator II = Use->use_begin(),
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EE = Use->use_end(); II != EE; ++II) {
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SDNode *UseUse = *II;
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if (UseUse->getOpcode() == ISD::LOAD &&
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cast<LoadSDNode>(UseUse)->getBasePtr().Val == Use)
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return false;
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else if (UseUse->getOpcode() == ISD::STORE &&
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cast<StoreSDNode>(UseUse)->getBasePtr().Val == Use)
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return false;
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}
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}
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}
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// 2) All uses are load / store ops that use it as base ptr.
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// Now check for #1 and #2.
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if (OffIsAMImm) {
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unsigned NumRealUses = 0;
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for (SDNode::use_iterator I = Ptr.Val->use_begin(),
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E = Ptr.Val->use_end(); I != E; ++I) {
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SDNode *Use = *I;
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if (Use == N)
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continue;
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if (Use->isPredecessor(N))
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return false;
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if (!OffIsAMImm) {
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NumRealUses++;
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} else if (Use->getOpcode() == ISD::LOAD) {
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if (cast<LoadSDNode>(Use)->getBasePtr().Val != Ptr.Val)
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NumRealUses++;
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} else if (Use->getOpcode() == ISD::STORE) {
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if (cast<StoreSDNode>(Use)->getBasePtr().Val != Ptr.Val)
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NumRealUses++;
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} else
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NumRealUses++;
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}
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if (NumRealUses == 0)
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bool RealUse = false;
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for (SDNode::use_iterator I = Ptr.Val->use_begin(),
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E = Ptr.Val->use_end(); I != E; ++I) {
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SDNode *Use = *I;
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if (Use == N)
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continue;
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if (Use->isPredecessor(N))
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return false;
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if (!((Use->getOpcode() == ISD::LOAD &&
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cast<LoadSDNode>(Use)->getBasePtr() == Ptr) ||
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(Use->getOpcode() == ISD::STORE) &&
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cast<StoreSDNode>(Use)->getBasePtr() == Ptr))
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RealUse = true;
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}
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if (!RealUse)
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return false;
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SDOperand Result = isLoad
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? DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM)
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@ -343,12 +308,7 @@ namespace {
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// 1) Op must be independent of N, i.e. Op is neither a predecessor
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// nor a successor of N. Otherwise, if Op is folded that would
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// create a cycle.
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// 2) All uses are load / store ops that use it as base ptr and offset
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// is just an addressing mode immediate.
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// 3) If the would-be new base may not to be dead at N.
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bool OffIsAMImm = Offset.getOpcode() == ISD::Constant && TLI.
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isLegalAddressImmediate(cast<ConstantSDNode>(Offset)->getValue());
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// 2) All uses are load / store ops that use it as base ptr.
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// Check for #3.
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bool TryNext = false;
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@ -357,51 +317,30 @@ namespace {
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SDNode *Use = *II;
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if (Use == Ptr.Val)
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continue;
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if (Use->getOpcode() == ISD::CopyToReg) {
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TryNext = true;
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break;
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}
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if (OffIsAMImm && (Use->getOpcode() == ISD::ADD ||
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Use->getOpcode() == ISD::SUB)) {
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// If all the uses are load / store addresses, then don't do the
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// transformation.
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if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
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bool RealUse = false;
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for (SDNode::use_iterator III = Use->use_begin(),
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EEE = Use->use_end(); III != EEE; ++III) {
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SDNode *UseUse = *III;
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if (UseUse->getOpcode() == ISD::LOAD &&
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cast<LoadSDNode>(UseUse)->getBasePtr().Val == Use) {
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TryNext = true;
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break;
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} else if (UseUse->getOpcode() == ISD::STORE &&
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cast<StoreSDNode>(UseUse)->getBasePtr().Val == Use) {
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if (!((UseUse->getOpcode() == ISD::LOAD &&
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cast<LoadSDNode>(UseUse)->getBasePtr().Val == Use) ||
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(UseUse->getOpcode() == ISD::STORE) &&
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cast<StoreSDNode>(UseUse)->getBasePtr().Val == Use))
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RealUse = true;
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}
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TryNext = true;
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break;
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}
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if (!RealUse) {
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TryNext = true;
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break;
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}
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}
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}
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if (TryNext)
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continue;
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if (OffIsAMImm) {
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// Check for #2.
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unsigned NumRealUses = 0;
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for (SDNode::use_iterator II = Op->use_begin(), EE = Op->use_end();
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II != EE; ++II) {
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SDNode *Use = *II;
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if (Use->getOpcode() == ISD::LOAD) {
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if (cast<LoadSDNode>(Use)->getBasePtr().Val != Op)
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NumRealUses++;
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} else if (Use->getOpcode() == ISD::STORE) {
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if (cast<StoreSDNode>(Use)->getBasePtr().Val != Op)
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NumRealUses++;
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} else
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NumRealUses++;
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}
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if (NumRealUses == 0)
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continue;
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}
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// Check for #1
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if (!Op->isPredecessor(N) && !N->isPredecessor(Op)) {
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SDOperand Result = isLoad
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