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R600/SI: remove some more unused code
This is a candidate for the stable branch. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175350 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1,45 +0,0 @@
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//===-- AMDGPUCodeEmitter.h - AMDGPU Code Emitter interface -----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief CodeEmitter interface for R600 and SI codegen.
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//
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//===----------------------------------------------------------------------===//
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#ifndef AMDGPUCODEEMITTER_H
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#define AMDGPUCODEEMITTER_H
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namespace llvm {
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class AMDGPUCodeEmitter {
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public:
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uint64_t getBinaryCodeForInstr(const MachineInstr &MI) const;
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virtual uint64_t getMachineOpValue(const MachineInstr &MI,
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const MachineOperand &MO) const { return 0; }
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virtual unsigned GPR4AlignEncode(const MachineInstr &MI,
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unsigned OpNo) const {
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return 0;
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}
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virtual unsigned GPR2AlignEncode(const MachineInstr &MI,
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unsigned OpNo) const {
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return 0;
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}
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virtual uint64_t VOPPostEncode(const MachineInstr &MI,
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uint64_t Value) const {
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return Value;
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}
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virtual uint64_t i32LiteralEncode(const MachineInstr &MI,
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unsigned OpNo) const {
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return 0;
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}
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};
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} // End namespace llvm
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#endif // AMDGPUCODEEMITTER_H
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@ -42,13 +42,6 @@ public:
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SmallVectorImpl<MCFixup> &Fixups) const {
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SmallVectorImpl<MCFixup> &Fixups) const {
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return 0;
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return 0;
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}
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}
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virtual uint64_t VOPPostEncode(const MCInst &MI, uint64_t Value) const {
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return Value;
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}
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virtual uint64_t i32LiteralEncode(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups) const {
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return 0;
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}
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};
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};
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} // End namespace llvm
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} // End namespace llvm
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