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Prevent ARM DAG Combiner from doing an AND or OR combine on an illegal vector type (vectors of size 3). Also included test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129074 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -5390,6 +5390,9 @@ static SDValue PerformANDCombine(SDNode *N,
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EVT VT = N->getValueType(0);
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SelectionDAG &DAG = DCI.DAG;
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if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
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return SDValue();
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APInt SplatBits, SplatUndef;
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unsigned SplatBitSize;
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bool HasAnyUndefs;
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@ -5423,6 +5426,9 @@ static SDValue PerformORCombine(SDNode *N,
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EVT VT = N->getValueType(0);
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SelectionDAG &DAG = DCI.DAG;
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if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
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return SDValue();
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APInt SplatBits, SplatUndef;
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unsigned SplatBitSize;
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bool HasAnyUndefs;
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@ -105,3 +105,21 @@ define void @i64_extractelement(i64* %ptr, <2 x i64>* %vp) nounwind {
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store i64 %t1, i64* %ptr
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ret void
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}
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; Test trying to do a AND Combine on illegal types.
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define void @andVec(<3 x i8>* %A) nounwind {
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%tmp = load <3 x i8>* %A, align 4
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%and = and <3 x i8> %tmp, <i8 7, i8 7, i8 7>
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store <3 x i8> %and, <3 x i8>* %A
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ret void
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}
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; Test trying to do an OR Combine on illegal types.
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define void @orVec(<3 x i8>* %A) nounwind {
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%tmp = load <3 x i8>* %A, align 4
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%or = or <3 x i8> %tmp, <i8 7, i8 7, i8 7>
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store <3 x i8> %or, <3 x i8>* %A
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ret void
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}
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