mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-22 10:29:35 +00:00
Prevent ARM DAG Combiner from doing an AND or OR combine on an illegal vector type (vectors of size 3). Also included test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129074 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
71001c97c6
commit
0433b21c98
@ -5390,6 +5390,9 @@ static SDValue PerformANDCombine(SDNode *N,
|
|||||||
EVT VT = N->getValueType(0);
|
EVT VT = N->getValueType(0);
|
||||||
SelectionDAG &DAG = DCI.DAG;
|
SelectionDAG &DAG = DCI.DAG;
|
||||||
|
|
||||||
|
if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
|
||||||
|
return SDValue();
|
||||||
|
|
||||||
APInt SplatBits, SplatUndef;
|
APInt SplatBits, SplatUndef;
|
||||||
unsigned SplatBitSize;
|
unsigned SplatBitSize;
|
||||||
bool HasAnyUndefs;
|
bool HasAnyUndefs;
|
||||||
@ -5423,6 +5426,9 @@ static SDValue PerformORCombine(SDNode *N,
|
|||||||
EVT VT = N->getValueType(0);
|
EVT VT = N->getValueType(0);
|
||||||
SelectionDAG &DAG = DCI.DAG;
|
SelectionDAG &DAG = DCI.DAG;
|
||||||
|
|
||||||
|
if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
|
||||||
|
return SDValue();
|
||||||
|
|
||||||
APInt SplatBits, SplatUndef;
|
APInt SplatBits, SplatUndef;
|
||||||
unsigned SplatBitSize;
|
unsigned SplatBitSize;
|
||||||
bool HasAnyUndefs;
|
bool HasAnyUndefs;
|
||||||
|
@ -105,3 +105,21 @@ define void @i64_extractelement(i64* %ptr, <2 x i64>* %vp) nounwind {
|
|||||||
store i64 %t1, i64* %ptr
|
store i64 %t1, i64* %ptr
|
||||||
ret void
|
ret void
|
||||||
}
|
}
|
||||||
|
|
||||||
|
; Test trying to do a AND Combine on illegal types.
|
||||||
|
define void @andVec(<3 x i8>* %A) nounwind {
|
||||||
|
%tmp = load <3 x i8>* %A, align 4
|
||||||
|
%and = and <3 x i8> %tmp, <i8 7, i8 7, i8 7>
|
||||||
|
store <3 x i8> %and, <3 x i8>* %A
|
||||||
|
ret void
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
; Test trying to do an OR Combine on illegal types.
|
||||||
|
define void @orVec(<3 x i8>* %A) nounwind {
|
||||||
|
%tmp = load <3 x i8>* %A, align 4
|
||||||
|
%or = or <3 x i8> %tmp, <i8 7, i8 7, i8 7>
|
||||||
|
store <3 x i8> %or, <3 x i8>* %A
|
||||||
|
ret void
|
||||||
|
}
|
||||||
|
|
||||||
|
Loading…
Reference in New Issue
Block a user