diff --git a/include/llvm/Target/TargetInstrDesc.h b/include/llvm/Target/TargetInstrDesc.h index b389a4f746c..622a216c33c 100644 --- a/include/llvm/Target/TargetInstrDesc.h +++ b/include/llvm/Target/TargetInstrDesc.h @@ -199,6 +199,24 @@ public: const unsigned *getImplicitDefs() const { return ImplicitDefs; } + + /// hasImplicitUseOfPhysReg - Return true if this instruction implicitly + /// uses the specified physical register. + bool hasImplicitUseOfPhysReg(unsigned Reg) const { + if (const unsigned *ImpUses = ImplicitUses) + for (; *ImpUses; ++ImpUses) + if (*ImpUses == Reg) return true; + return false; + } + + /// hasImplicitDefOfPhysReg - Return true if this instruction implicitly + /// defines the specified physical register. + bool hasImplicitDefOfPhysReg(unsigned Reg) const { + if (const unsigned *ImpDefs = ImplicitDefs) + for (; *ImpDefs; ++ImpDefs) + if (*ImpDefs == Reg) return true; + return false; + } /// getRegClassBarriers - Return a list of register classes that are /// completely clobbered by this machine instruction. For example, on X86 diff --git a/lib/Target/X86/X86FastISel.cpp b/lib/Target/X86/X86FastISel.cpp index 7b114ddbc38..0146b0730de 100644 --- a/lib/Target/X86/X86FastISel.cpp +++ b/lib/Target/X86/X86FastISel.cpp @@ -808,21 +808,9 @@ bool X86FastISel::X86SelectBranch(Instruction *I) { } const TargetInstrDesc &TID = MI.getDesc(); - const unsigned *ImpDefs = TID.getImplicitDefs(); - - if (TID.hasUnmodeledSideEffects()) break; - - bool ModifiesEFlags = false; - - if (ImpDefs) { - for (unsigned u = 0; ImpDefs[u]; ++u) - if (ImpDefs[u] == X86::EFLAGS) { - ModifiesEFlags = true; - break; - } - } - - if (ModifiesEFlags) break; + if (TID.hasUnmodeledSideEffects() || + TID.hasImplicitDefOfPhysReg(X86::EFLAGS)) + break; } if (SetMI) {