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Change weight array into a vector and make it as big as the number of

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registers (not as the max number of registers).

Change toSpill from a std::set into a std::vector<bool>.

Use the reverse iterator adapter to do a reverse scan of allocatable
registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11061 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Alkis Evlogimenos 2004-02-01 20:13:26 +00:00
parent f440cc19c9
commit 04667297af
1 changed files with 25 additions and 17 deletions
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42
lib/CodeGen/RegAllocLinearScan.cpp
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@ -75,10 +75,12 @@ namespace {
MachineFunctionPass::getAnalysisUsage(AU); MachineFunctionPass::getAnalysisUsage(AU);
} }
private:
/// runOnMachineFunction - register allocate the whole function /// runOnMachineFunction - register allocate the whole function
bool runOnMachineFunction(MachineFunction&); bool runOnMachineFunction(MachineFunction&);
void releaseMemory();
private:
/// initIntervalSets - initializa the four interval sets: /// initIntervalSets - initializa the four interval sets:
/// unhandled, fixed, active and inactive /// unhandled, fixed, active and inactive
void initIntervalSets(const LiveIntervals::Intervals& li); void initIntervalSets(const LiveIntervals::Intervals& li);
@ -202,6 +204,17 @@ namespace {
}; };
} }
void RA::releaseMemory()
{
v2pMap_.clear();
v2ssMap_.clear();
unhandled_.clear();
active_.clear();
inactive_.clear();
fixed_.clear();
}
bool RA::runOnMachineFunction(MachineFunction &fn) { bool RA::runOnMachineFunction(MachineFunction &fn) {
mf_ = &fn; mf_ = &fn;
tm_ = &fn.getTarget(); tm_ = &fn.getTarget();
@ -209,8 +222,6 @@ bool RA::runOnMachineFunction(MachineFunction &fn) {
li_ = &getAnalysis<LiveIntervals>(); li_ = &getAnalysis<LiveIntervals>();
initIntervalSets(li_->getIntervals()); initIntervalSets(li_->getIntervals());
v2pMap_.clear();
v2ssMap_.clear();
memset(regUse_, 0, sizeof(regUse_)); memset(regUse_, 0, sizeof(regUse_));
memset(regUseBackup_, 0, sizeof(regUseBackup_)); memset(regUseBackup_, 0, sizeof(regUseBackup_));
@ -325,8 +336,6 @@ bool RA::runOnMachineFunction(MachineFunction &fn) {
} }
markPhysRegFree(reg); markPhysRegFree(reg);
} }
active_.clear();
inactive_.clear();
typedef LiveIntervals::Reg2RegMap Reg2RegMap; typedef LiveIntervals::Reg2RegMap Reg2RegMap;
const Reg2RegMap& r2rMap = li_->getJoinedRegMap(); const Reg2RegMap& r2rMap = li_->getJoinedRegMap();
@ -559,7 +568,7 @@ void RA::processInactiveIntervals(IntervalPtrs::value_type cur)
namespace { namespace {
template <typename T> template <typename T>
void updateWeight(T rw[], int reg, T w) void updateWeight(std::vector<T>& rw, int reg, T w)
{ {
if (rw[reg] == std::numeric_limits<T>::max() || if (rw[reg] == std::numeric_limits<T>::max() ||
w == std::numeric_limits<T>::max()) w == std::numeric_limits<T>::max())
@ -574,10 +583,7 @@ void RA::assignStackSlotAtInterval(IntervalPtrs::value_type cur)
DEBUG(std::cerr << "\t\tassigning stack slot at interval " DEBUG(std::cerr << "\t\tassigning stack slot at interval "
<< *cur << ":\n"); << *cur << ":\n");
// set all weights to zero std::vector<float> regWeight(mri_->getNumRegs(), 0.0);
float regWeight[MRegisterInfo::FirstVirtualRegister];
for (unsigned i = 0; i < MRegisterInfo::FirstVirtualRegister; ++i)
regWeight[i] = 0.0F;
// for each interval in active // for each interval in active
for (IntervalPtrs::const_iterator i = active_.begin(), e = active_.end(); for (IntervalPtrs::const_iterator i = active_.begin(), e = active_.end();
@ -639,17 +645,17 @@ void RA::assignStackSlotAtInterval(IntervalPtrs::value_type cur)
assignVirt2StackSlot(cur->reg); assignVirt2StackSlot(cur->reg);
} }
else { else {
std::set<unsigned> toSpill; std::vector<bool> toSpill(mri_->getNumRegs(), false);
toSpill.insert(minReg); toSpill[minReg] = true;
for (const unsigned* as = mri_->getAliasSet(minReg); *as; ++as) for (const unsigned* as = mri_->getAliasSet(minReg); *as; ++as)
toSpill.insert(*as); toSpill[*as] = true;
std::vector<unsigned> spilled; std::vector<unsigned> spilled;
for (IntervalPtrs::iterator i = active_.begin(); for (IntervalPtrs::iterator i = active_.begin();
i != active_.end(); ) { i != active_.end(); ) {
unsigned reg = (*i)->reg; unsigned reg = (*i)->reg;
if (MRegisterInfo::isVirtualRegister(reg) && if (MRegisterInfo::isVirtualRegister(reg) &&
toSpill.find(v2pMap_[reg]) != toSpill.end() && toSpill[v2pMap_[reg]] &&
cur->overlaps(**i)) { cur->overlaps(**i)) {
spilled.push_back(v2pMap_[reg]); spilled.push_back(v2pMap_[reg]);
DEBUG(std::cerr << "\t\t\t\tspilling : " << **i << '\n'); DEBUG(std::cerr << "\t\t\t\tspilling : " << **i << '\n');
@ -664,7 +670,7 @@ void RA::assignStackSlotAtInterval(IntervalPtrs::value_type cur)
i != inactive_.end(); ) { i != inactive_.end(); ) {
unsigned reg = (*i)->reg; unsigned reg = (*i)->reg;
if (MRegisterInfo::isVirtualRegister(reg) && if (MRegisterInfo::isVirtualRegister(reg) &&
toSpill.find(v2pMap_[reg]) != toSpill.end() && toSpill[v2pMap_[reg]] &&
cur->overlaps(**i)) { cur->overlaps(**i)) {
DEBUG(std::cerr << "\t\t\t\tspilling : " << **i << '\n'); DEBUG(std::cerr << "\t\t\t\tspilling : " << **i << '\n');
assignVirt2StackSlot(reg); assignVirt2StackSlot(reg);
@ -727,8 +733,10 @@ unsigned RA::getFreeTempPhysReg(unsigned virtReg)
const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(virtReg); const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(virtReg);
// go in reverse allocation order for the temp registers // go in reverse allocation order for the temp registers
for (TargetRegisterClass::iterator i = rc->allocation_order_end(*mf_) - 1; typedef std::reverse_iterator<TargetRegisterClass::iterator> TRCRevIter;
i != rc->allocation_order_begin(*mf_) - 1; --i) { for (TRCRevIter
i(rc->allocation_order_end(*mf_)),
e(rc->allocation_order_begin(*mf_)); i != e; ++i) {
unsigned reg = *i; unsigned reg = *i;
if (reserved_[reg] && !regUse_[reg]) { if (reserved_[reg] && !regUse_[reg]) {
DEBUG(std::cerr << mri_->getName(reg) << '\n'); DEBUG(std::cerr << mri_->getName(reg) << '\n');