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Minor cleanups:

Browse Source 
- Get the opcode once.
- Add a ParserMatchClass to reglist.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118997 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling 2010-11-13 10:40:19 +00:00
parent 6c470b806f
commit 04863d06fb
2 changed files with 14 additions and 11 deletions
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11
lib/Target/ARM/ARMInstrInfo.td
View File

@ -285,16 +285,17 @@ def bltarget : Operand<i32> {
}
// A list of registers separated by comma. Used by load/store multiple.
def reglist : Operand<i32> {
string EncoderMethod = "getRegisterListOpValue";
let PrintMethod = "printRegisterList";
}
def RegListAsmOperand : AsmOperandClass {
let Name = "RegList";
let SuperClasses = [];
}
def reglist : Operand<i32> {
string EncoderMethod = "getRegisterListOpValue";
let ParserMatchClass = RegListAsmOperand;
let PrintMethod = "printRegisterList";
}
// An operand for the CONSTPOOL_ENTRY pseudo-instruction.
def cpinst_operand : Operand<i32> {
let PrintMethod = "printCPInstOperand";

14
lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
View File

@ -31,8 +31,10 @@ StringRef ARMInstPrinter::getOpcodeName(unsigned Opcode) const {
void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
unsigned Opcode = MI->getOpcode();
// Check for MOVs and print canonical forms, instead.
if (MI->getOpcode() == ARM::MOVs) {
if (Opcode == ARM::MOVs) {
// FIXME: Thumb variants?
const MCOperand &Dst = MI->getOperand(0);
const MCOperand &MO1 = MI->getOperand(1);
@ -61,7 +63,7 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
}
// A8.6.123 PUSH
if ((MI->getOpcode() == ARM::STM_UPD || MI->getOpcode() == ARM::t2STM_UPD) &&
if ((Opcode == ARM::STM_UPD || Opcode == ARM::t2STM_UPD) &&
MI->getOperand(0).getReg() == ARM::SP) {
const MCOperand &MO1 = MI->getOperand(2);
if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::db) {
@ -74,7 +76,7 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
}
// A8.6.122 POP
if ((MI->getOpcode() == ARM::LDM_UPD || MI->getOpcode() == ARM::t2LDM_UPD) &&
if ((Opcode == ARM::LDM_UPD || Opcode == ARM::t2LDM_UPD) &&
MI->getOperand(0).getReg() == ARM::SP) {
const MCOperand &MO1 = MI->getOperand(2);
if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::ia) {
@ -87,7 +89,7 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
}
// A8.6.355 VPUSH
if ((MI->getOpcode() == ARM::VSTMS_UPD || MI->getOpcode() ==ARM::VSTMD_UPD) &&
if ((Opcode == ARM::VSTMS_UPD || Opcode == ARM::VSTMD_UPD) &&
MI->getOperand(0).getReg() == ARM::SP) {
const MCOperand &MO1 = MI->getOperand(2);
if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::db) {
@ -100,7 +102,7 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
}
// A8.6.354 VPOP
if ((MI->getOpcode() == ARM::VLDMS_UPD || MI->getOpcode() ==ARM::VLDMD_UPD) &&
if ((Opcode == ARM::VLDMS_UPD || Opcode == ARM::VLDMD_UPD) &&
MI->getOperand(0).getReg() == ARM::SP) {
const MCOperand &MO1 = MI->getOperand(2);
if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::ia) {
@ -113,7 +115,7 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
}
printInstruction(MI, O);
}
}
void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {