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Handle sub-register operands in recomputeRegClass().

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Now that getMatchingSuperRegClass() returns accurate results, it can be
used to compute constraints imposed by instructions using a sub-register
of a virtual register.

This means we can recompute the register class of any virtual register
by combining the constraints from all its uses.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146874 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
2011-12-19 16:53:37 +00:00
parent 570f9a972e
commit 0488d6ee5d
1 changed files with 6 additions and 4 deletions
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10
lib/CodeGen/MachineRegisterInfo.cpp
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@ -76,12 +76,14 @@ MachineRegisterInfo::recomputeRegClass(unsigned Reg, const TargetMachine &TM) {
// Accumulate constraints from all uses. // Accumulate constraints from all uses.
for (reg_nodbg_iterator I = reg_nodbg_begin(Reg), E = reg_nodbg_end(); I != E; for (reg_nodbg_iterator I = reg_nodbg_begin(Reg), E = reg_nodbg_end(); I != E;
++I) { ++I) {
// TRI doesn't have accurate enough information to model this yet.
if (I.getOperand().getSubReg())
return false;
const TargetRegisterClass *OpRC = const TargetRegisterClass *OpRC =
I->getRegClassConstraint(I.getOperandNo(), TII, TRI); I->getRegClassConstraint(I.getOperandNo(), TII, TRI);
if (OpRC) if (unsigned SubIdx = I.getOperand().getSubReg()) {
if (OpRC)
NewRC = TRI->getMatchingSuperRegClass(NewRC, OpRC, SubIdx);
else
NewRC = TRI->getSubClassWithSubReg(NewRC, SubIdx);
} else if (OpRC)
NewRC = TRI->getCommonSubClass(NewRC, OpRC); NewRC = TRI->getCommonSubClass(NewRC, OpRC);
if (!NewRC || NewRC == OldRC) if (!NewRC || NewRC == OldRC)
return false; return false;