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Handle sub-register operands in recomputeRegClass().
Now that getMatchingSuperRegClass() returns accurate results, it can be used to compute constraints imposed by instructions using a sub-register of a virtual register. This means we can recompute the register class of any virtual register by combining the constraints from all its uses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146874 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -76,12 +76,14 @@ MachineRegisterInfo::recomputeRegClass(unsigned Reg, const TargetMachine &TM) {
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// Accumulate constraints from all uses.
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for (reg_nodbg_iterator I = reg_nodbg_begin(Reg), E = reg_nodbg_end(); I != E;
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++I) {
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// TRI doesn't have accurate enough information to model this yet.
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if (I.getOperand().getSubReg())
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return false;
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const TargetRegisterClass *OpRC =
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I->getRegClassConstraint(I.getOperandNo(), TII, TRI);
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if (unsigned SubIdx = I.getOperand().getSubReg()) {
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if (OpRC)
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NewRC = TRI->getMatchingSuperRegClass(NewRC, OpRC, SubIdx);
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else
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NewRC = TRI->getSubClassWithSubReg(NewRC, SubIdx);
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} else if (OpRC)
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NewRC = TRI->getCommonSubClass(NewRC, OpRC);
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if (!NewRC || NewRC == OldRC)
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return false;
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