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https://github.com/c64scene-ar/llvm-6502.git
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R600/SI: Use source modifiers for f64 fneg
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215748 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault
parent
c882fc78fe
commit
0498d07255
@ -446,7 +446,7 @@ bool AMDGPUTargetLowering::isFAbsFree(EVT VT) const {
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bool AMDGPUTargetLowering::isFNegFree(EVT VT) const {
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assert(VT.isFloatingPoint());
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return VT == MVT::f32;
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return VT == MVT::f32 || VT == MVT::f64;
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}
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bool AMDGPUTargetLowering::isTruncateFree(EVT Source, EVT Dest) const {
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@ -223,10 +223,6 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) :
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setOperationAction(ISD::FRINT, MVT::f64, Legal);
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}
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// FIXME: These should be removed and handled the same was as f32 fneg. Source
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// modifiers also work for the double instructions.
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setOperationAction(ISD::FNEG, MVT::f64, Expand);
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setOperationAction(ISD::FDIV, MVT::f32, Custom);
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setTargetDAGCombine(ISD::SELECT_CC);
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@ -701,6 +697,7 @@ MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
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unsigned DestReg = MI->getOperand(0).getReg();
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unsigned Reg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
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// FIXME: Should use SALU instructions
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BuildMI(*BB, I, DL, TII->get(AMDGPU::V_MOV_B32_e32), Reg)
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.addImm(0x80000000);
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BuildMI(*BB, I, DL, TII->get(AMDGPU::V_XOR_B32_e32), DestReg)
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@ -709,6 +706,33 @@ MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
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MI->eraseFromParent();
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break;
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}
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case AMDGPU::FNEG64_SI: {
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MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
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const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(
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getTargetMachine().getSubtargetImpl()->getInstrInfo());
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DebugLoc DL = MI->getDebugLoc();
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unsigned SrcReg = MI->getOperand(1).getReg();
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unsigned DestReg = MI->getOperand(0).getReg();
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unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
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unsigned ImmReg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
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// FIXME: Should use SALU instructions
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BuildMI(*BB, I, DL, TII->get(AMDGPU::V_MOV_B32_e32), ImmReg)
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.addImm(0x80000000);
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BuildMI(*BB, I, DL, TII->get(AMDGPU::V_XOR_B32_e32), TmpReg)
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.addReg(SrcReg, 0, AMDGPU::sub1)
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.addReg(ImmReg);
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BuildMI(*BB, I, DL, TII->get(AMDGPU::REG_SEQUENCE), DestReg)
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.addReg(SrcReg, 0, AMDGPU::sub0)
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.addImm(AMDGPU::sub0)
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.addReg(TmpReg)
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.addImm(AMDGPU::sub1);
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MI->eraseFromParent();
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break;
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}
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case AMDGPU::FCLAMP_SI: {
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const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(
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getTargetMachine().getSubtargetImpl()->getInstrInfo());
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@ -2328,12 +2328,20 @@ def : Pat <
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// TODO: Look into not implementing isFNegFree/isFAbsFree for SI, and possibly
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// removing these patterns
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def : Pat <
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(fneg (fabs f32:$src)),
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(V_OR_B32_e32 $src, (V_MOV_B32_e32 0x80000000)) /* Set sign bit */
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>;
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def : Pat <
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(fneg (fabs f64:$src)),
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(f64 (INSERT_SUBREG
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(INSERT_SUBREG (f64 (IMPLICIT_DEF)),
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(i32 (EXTRACT_SUBREG f64:$src, sub0)), sub0),
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(V_OR_B32_e32 (S_MOV_B32 0x80000000),
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(EXTRACT_SUBREG f64:$src, sub1)), sub1)) // Set sign bit.
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>;
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class SIUnaryCustomInsertInst<string name, SDPatternOperator node,
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ValueType vt,
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RegisterClass dstrc,
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89
test/CodeGen/R600/fneg-fabs.f64.ll
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89
test/CodeGen/R600/fneg-fabs.f64.ll
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@ -0,0 +1,89 @@
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; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; FIXME: Check something here. Currently it seems fabs + fneg aren't
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; into 2 modifiers, although theoretically that should work.
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; FUNC-LABEL: @fneg_fabs_fadd_f64
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; SI: V_AND_B32_e32 v[[FABS:[0-9]+]], 0x7fffffff, {{v[0-9]+}}
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; SI: V_ADD_F64 {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, -v{{\[[0-9]+}}:[[FABS]]{{\]}}
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define void @fneg_fabs_fadd_f64(double addrspace(1)* %out, double %x, double %y) {
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%fabs = call double @llvm.fabs.f64(double %x)
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%fsub = fsub double -0.000000e+00, %fabs
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%fadd = fadd double %y, %fsub
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store double %fadd, double addrspace(1)* %out, align 8
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ret void
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}
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define void @v_fneg_fabs_fadd_f64(double addrspace(1)* %out, double addrspace(1)* %xptr, double addrspace(1)* %yptr) {
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%x = load double addrspace(1)* %xptr, align 8
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%y = load double addrspace(1)* %xptr, align 8
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%fabs = call double @llvm.fabs.f64(double %x)
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%fsub = fsub double -0.000000e+00, %fabs
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%fadd = fadd double %y, %fsub
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store double %fadd, double addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: @fneg_fabs_fmul_f64
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; SI: V_MUL_F64 {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, -|{{v\[[0-9]+:[0-9]+\]}}|
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define void @fneg_fabs_fmul_f64(double addrspace(1)* %out, double %x, double %y) {
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%fabs = call double @llvm.fabs.f64(double %x)
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%fsub = fsub double -0.000000e+00, %fabs
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%fmul = fmul double %y, %fsub
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store double %fmul, double addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: @fneg_fabs_free_f64
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define void @fneg_fabs_free_f64(double addrspace(1)* %out, i64 %in) {
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%bc = bitcast i64 %in to double
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%fabs = call double @llvm.fabs.f64(double %bc)
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%fsub = fsub double -0.000000e+00, %fabs
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store double %fsub, double addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: @fneg_fabs_fn_free_f64
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; SI: V_OR_B32_e32 v{{[0-9]+}}, 0x80000000, v{{[0-9]+}}
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define void @fneg_fabs_fn_free_f64(double addrspace(1)* %out, i64 %in) {
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%bc = bitcast i64 %in to double
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%fabs = call double @fabs(double %bc)
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%fsub = fsub double -0.000000e+00, %fabs
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store double %fsub, double addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: @fneg_fabs_f64
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define void @fneg_fabs_f64(double addrspace(1)* %out, double %in) {
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%fabs = call double @llvm.fabs.f64(double %in)
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%fsub = fsub double -0.000000e+00, %fabs
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store double %fsub, double addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: @fneg_fabs_v2f64
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; SI: V_OR_B32_e32 v{{[0-9]+}}, 0x80000000, v{{[0-9]+}}
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; SI: V_OR_B32_e32 v{{[0-9]+}}, 0x80000000, v{{[0-9]+}}
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define void @fneg_fabs_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %in) {
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%fabs = call <2 x double> @llvm.fabs.v2f64(<2 x double> %in)
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%fsub = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %fabs
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store <2 x double> %fsub, <2 x double> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: @fneg_fabs_v4f64
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; SI: V_OR_B32_e32 v{{[0-9]+}}, 0x80000000, v{{[0-9]+}}
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; SI: V_OR_B32_e32 v{{[0-9]+}}, 0x80000000, v{{[0-9]+}}
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; SI: V_OR_B32_e32 v{{[0-9]+}}, 0x80000000, v{{[0-9]+}}
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; SI: V_OR_B32_e32 v{{[0-9]+}}, 0x80000000, v{{[0-9]+}}
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define void @fneg_fabs_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %in) {
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%fabs = call <4 x double> @llvm.fabs.v4f64(<4 x double> %in)
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%fsub = fsub <4 x double> <double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>, %fabs
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store <4 x double> %fsub, <4 x double> addrspace(1)* %out
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ret void
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}
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declare double @fabs(double) readnone
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declare double @llvm.fabs.f64(double) readnone
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declare <2 x double> @llvm.fabs.v2f64(<2 x double>) readnone
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declare <4 x double> @llvm.fabs.v4f64(<4 x double>) readnone
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59
test/CodeGen/R600/fneg.f64.ll
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59
test/CodeGen/R600/fneg.f64.ll
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@ -0,0 +1,59 @@
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; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; FUNC-LABEL: @fneg_f64
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; SI: V_XOR_B32
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define void @fneg_f64(double addrspace(1)* %out, double %in) {
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%fneg = fsub double -0.000000e+00, %in
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store double %fneg, double addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: @fneg_v2f64
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; SI: V_XOR_B32
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; SI: V_XOR_B32
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define void @fneg_v2f64(<2 x double> addrspace(1)* nocapture %out, <2 x double> %in) {
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%fneg = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %in
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store <2 x double> %fneg, <2 x double> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: @fneg_v4f64
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; R600: -PV
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; R600: -T
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; R600: -PV
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; R600: -PV
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; SI: V_XOR_B32
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; SI: V_XOR_B32
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; SI: V_XOR_B32
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; SI: V_XOR_B32
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define void @fneg_v4f64(<4 x double> addrspace(1)* nocapture %out, <4 x double> %in) {
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%fneg = fsub <4 x double> <double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>, %in
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store <4 x double> %fneg, <4 x double> addrspace(1)* %out
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ret void
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}
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; DAGCombiner will transform:
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; (fneg (f64 bitcast (i64 a))) => (f64 bitcast (xor (i64 a), 0x80000000))
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; unless the target returns true for isNegFree()
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; FUNC-LABEL: @fneg_free_f64
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; FIXME: Unnecessary copy to VGPRs
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; SI: V_ADD_F64 {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, -{{v\[[0-9]+:[0-9]+\]}}, 0, 0
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define void @fneg_free_f64(double addrspace(1)* %out, i64 %in) {
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%bc = bitcast i64 %in to double
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%fsub = fsub double 0.0, %bc
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store double %fsub, double addrspace(1)* %out
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ret void
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}
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; SI-LABEL: @fneg_fold
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; SI: S_LOAD_DWORDX2 [[NEG_VALUE:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
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; SI-NOT: XOR
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; SI: V_MUL_F64 {{v\[[0-9]+:[0-9]+\]}}, -[[NEG_VALUE]], {{v\[[0-9]+:[0-9]+\]}}
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define void @fneg_fold_f64(double addrspace(1)* %out, double %in) {
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%fsub = fsub double -0.0, %in
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%fmul = fmul double %fsub, %in
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store double %fmul, double addrspace(1)* %out
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ret void
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}
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