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[x86] Prevent instruction selection of AVX512 cmp.ps/pd/ss/sd intrinsics with illegal immediates. Correctly this time. I did the wrong patterns the first time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224891 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
parent
bd64447bf3
commit
04c853b269
@ -1198,18 +1198,16 @@ def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
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// avx512_cmp_scalar - AVX512 CMPSS and CMPSD
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multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
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ValueType VT,
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Operand CC, SDNode OpNode, ValueType VT,
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PatFrag ld_frag, string asm, string asm_alt> {
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def rr : AVX512Ii8<0xC2, MRMSrcReg,
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(outs VK1:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc), asm,
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[(set VK1:$dst, (X86cmpms (VT RC:$src1),
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RC:$src2, i8immZExt5:$cc))],
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(outs VK1:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
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[(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
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IIC_SSE_ALU_F32S_RR>, EVEX_4V;
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def rm : AVX512Ii8<0xC2, MRMSrcMem,
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(outs VK1:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc), asm,
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[(set VK1:$dst, (X86cmpms (VT RC:$src1),
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(ld_frag addr:$src2), i8immZExt5:$cc))], IIC_SSE_ALU_F32P_RM>,
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EVEX_4V;
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(outs VK1:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
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[(set VK1:$dst, (OpNode (VT RC:$src1),
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(ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
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let isAsmParserOnly = 1, hasSideEffects = 0 in {
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def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
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(outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
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@ -1221,11 +1219,11 @@ multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
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}
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let Predicates = [HasAVX512] in {
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defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, f32, loadf32,
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defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, AVXCC, X86cmpms, f32, loadf32,
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"vcmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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"vcmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
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XS;
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defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, f64, loadf64,
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defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, AVXCC, X86cmpms, f64, loadf64,
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"vcmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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"vcmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
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XD, VEX_W;
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@ -1376,7 +1374,7 @@ multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
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"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
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(_.VT (bitconvert (_.LdFrag addr:$src2))),
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i8immZExt5:$cc))],
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imm:$cc))],
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IIC_SSE_ALU_F32P_RM>, EVEX_4V;
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def rrik : AVX512AIi8<opc, MRMSrcReg,
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(outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
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@ -1386,7 +1384,7 @@ multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
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"$dst {${mask}}, $src1, $src2}"),
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[(set _.KRC:$dst, (and _.KRCWM:$mask,
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(OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
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i8immZExt5:$cc)))],
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imm:$cc)))],
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IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
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let mayLoad = 1 in
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def rmik : AVX512AIi8<opc, MRMSrcMem,
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@ -1398,7 +1396,7 @@ multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
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[(set _.KRC:$dst, (and _.KRCWM:$mask,
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(OpNode (_.VT _.RC:$src1),
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(_.VT (bitconvert (_.LdFrag addr:$src2))),
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i8immZExt5:$cc)))],
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imm:$cc)))],
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IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
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// Accept explicit immediate argument form instead of comparison code.
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@ -1442,7 +1440,7 @@ multiclass avx512_icmp_cc_rmb<bits<8> opc, string Suffix, SDNode OpNode,
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"$dst, $src1, ${src2}", _.BroadcastStr, "}"),
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[(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
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(X86VBroadcast (_.ScalarLdFrag addr:$src2)),
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i8immZExt5:$cc))],
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imm:$cc))],
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IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
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def rmibk : AVX512AIi8<opc, MRMSrcMem,
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(outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
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@ -1453,7 +1451,7 @@ multiclass avx512_icmp_cc_rmb<bits<8> opc, string Suffix, SDNode OpNode,
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[(set _.KRC:$dst, (and _.KRCWM:$mask,
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(OpNode (_.VT _.RC:$src1),
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(X86VBroadcast (_.ScalarLdFrag addr:$src2)),
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i8immZExt5:$cc)))],
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imm:$cc)))],
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IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
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}
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@ -1529,8 +1527,7 @@ multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
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(outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
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!strconcat("vcmp${cc}", suffix,
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"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2),
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i8immZExt5:$cc))], d>;
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[(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
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def rrib: AVX512PIi8<0xC2, MRMSrcReg,
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(outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
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!strconcat("vcmp${cc}", suffix,
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@ -1541,7 +1538,7 @@ multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
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!strconcat("vcmp${cc}", suffix,
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"\t{$src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
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[(set KRC:$dst,
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(X86cmpm (vt RC:$src1), (memop addr:$src2), i8immZExt5:$cc))], d>;
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(X86cmpm (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
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// Accept explicit immediate argument form instead of comparison code.
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let isAsmParserOnly = 1, hasSideEffects = 0 in {
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@ -1580,25 +1577,25 @@ def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
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imm:$cc), VK8)>;
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def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
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(v16f32 VR512:$src2), imm:$cc, (i16 -1),
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(v16f32 VR512:$src2), i32immZExt5:$cc, (i16 -1),
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FROUND_NO_EXC)),
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(COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
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(I8Imm imm:$cc)), GR16)>;
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def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
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(v8f64 VR512:$src2), imm:$cc, (i8 -1),
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(v8f64 VR512:$src2), i32immZExt5:$cc, (i8 -1),
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FROUND_NO_EXC)),
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(COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
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(I8Imm imm:$cc)), GR8)>;
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def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
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(v16f32 VR512:$src2), imm:$cc, (i16 -1),
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(v16f32 VR512:$src2), i32immZExt5:$cc, (i16 -1),
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FROUND_CURRENT)),
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(COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
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(I8Imm imm:$cc)), GR16)>;
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def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
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(v8f64 VR512:$src2), imm:$cc, (i8 -1),
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(v8f64 VR512:$src2), i32immZExt5:$cc, (i8 -1),
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FROUND_CURRENT)),
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(COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
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(I8Imm imm:$cc)), GR8)>;
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@ -553,6 +553,10 @@ def AVXCC : Operand<i8> {
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def i8immZExt5 : ImmLeaf<i8, [{
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return Imm >= 0 && Imm < 32;
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}]>;
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// AVX-512 uses a 32-bit immediate in their intrinsics
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def i32immZExt5 : ImmLeaf<i32, [{
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return Imm >= 0 && Imm < 32;
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}]>;
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class ImmSExtAsmOperandClass : AsmOperandClass {
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let SuperClasses = [ImmAsmOperand];
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