mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-19 03:29:22 +00:00
Claiming that branch targets are registers is not very wholesome. Change them
to be basic blocks. Also, add uncond branches. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24810 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
456b9400dc
commit
04dd673aea
@ -68,12 +68,16 @@ def MEMri : Operand<i32> {
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let MIOperandInfo = (ops IntRegs, i32imm);
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}
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// Branch targets have OtherVT type.
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def brtarget : Operand<OtherVT>;
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def SDTV8cmpicc :
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SDTypeProfile<1, 2, [SDTCisVT<0, FlagVT>, SDTCisInt<1>, SDTCisSameAs<1, 2>]>;
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def SDTV8cmpfcc :
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SDTypeProfile<1, 2, [SDTCisVT<0, FlagVT>, SDTCisFP<1>, SDTCisSameAs<1, 2>]>;
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def SDTV8brcc :
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SDTypeProfile<0, 3, [SDTCisInt<0>, SDTCisVT<1, OtherVT>, SDTCisVT<2, FlagVT>]>;
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SDTypeProfile<0, 3, [SDTCisVT<0, OtherVT>, SDTCisVT<1, OtherVT>,
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SDTCisVT<2, FlagVT>]>;
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def V8cmpicc : SDNode<"V8ISD::CMPICC", SDTV8cmpicc>;
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def V8cmpfcc : SDNode<"V8ISD::CMPFCC", SDTV8cmpfcc>;
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@ -410,38 +414,39 @@ class BranchV8<bits<4> cc, dag ops, string asmstr, list<dag> pattern>
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}
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let isBarrier = 1 in
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def BA : BranchV8<0b1000, (ops IntRegs:$dst),
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"ba $dst", []>;
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def BNE : BranchV8<0b1001, (ops IntRegs:$dst),
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def BA : BranchV8<0b1000, (ops brtarget:$dst),
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"ba $dst",
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[(br bb:$dst)]>;
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def BNE : BranchV8<0b1001, (ops brtarget:$dst),
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"bne $dst",
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[(V8bricc IntRegs:$dst, SETNE, ICC)]>;
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def BE : BranchV8<0b0001, (ops IntRegs:$dst),
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[(V8bricc bb:$dst, SETNE, ICC)]>;
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def BE : BranchV8<0b0001, (ops brtarget:$dst),
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"be $dst",
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[(V8bricc IntRegs:$dst, SETEQ, ICC)]>;
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def BG : BranchV8<0b1010, (ops IntRegs:$dst),
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[(V8bricc bb:$dst, SETEQ, ICC)]>;
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def BG : BranchV8<0b1010, (ops brtarget:$dst),
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"bg $dst",
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[(V8bricc IntRegs:$dst, SETGT, ICC)]>;
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def BLE : BranchV8<0b0010, (ops IntRegs:$dst),
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[(V8bricc bb:$dst, SETGT, ICC)]>;
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def BLE : BranchV8<0b0010, (ops brtarget:$dst),
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"ble $dst",
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[(V8bricc IntRegs:$dst, SETLE, ICC)]>;
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def BGE : BranchV8<0b1011, (ops IntRegs:$dst),
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[(V8bricc bb:$dst, SETLE, ICC)]>;
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def BGE : BranchV8<0b1011, (ops brtarget:$dst),
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"bge $dst",
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[(V8bricc IntRegs:$dst, SETGE, ICC)]>;
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def BL : BranchV8<0b0011, (ops IntRegs:$dst),
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[(V8bricc bb:$dst, SETGE, ICC)]>;
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def BL : BranchV8<0b0011, (ops brtarget:$dst),
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"bl $dst",
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[(V8bricc IntRegs:$dst, SETLT, ICC)]>;
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def BGU : BranchV8<0b1100, (ops IntRegs:$dst),
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[(V8bricc bb:$dst, SETLT, ICC)]>;
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def BGU : BranchV8<0b1100, (ops brtarget:$dst),
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"bgu $dst",
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[(V8bricc IntRegs:$dst, SETUGT, ICC)]>;
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def BLEU : BranchV8<0b0100, (ops IntRegs:$dst),
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[(V8bricc bb:$dst, SETUGT, ICC)]>;
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def BLEU : BranchV8<0b0100, (ops brtarget:$dst),
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"bleu $dst",
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[(V8bricc IntRegs:$dst, SETULE, ICC)]>;
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def BCC : BranchV8<0b1101, (ops IntRegs:$dst),
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[(V8bricc bb:$dst, SETULE, ICC)]>;
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def BCC : BranchV8<0b1101, (ops brtarget:$dst),
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"bcc $dst",
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[(V8bricc IntRegs:$dst, SETUGE, ICC)]>;
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def BCS : BranchV8<0b0101, (ops IntRegs:$dst),
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[(V8bricc bb:$dst, SETUGE, ICC)]>;
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def BCS : BranchV8<0b0101, (ops brtarget:$dst),
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"bcs $dst",
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[(V8bricc IntRegs:$dst, SETULT, ICC)]>;
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[(V8bricc bb:$dst, SETULT, ICC)]>;
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// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121
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@ -453,48 +458,48 @@ class FPBranchV8<bits<4> cc, dag ops, string asmstr, list<dag> pattern>
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let hasDelaySlot = 1;
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}
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def FBU : FPBranchV8<0b0111, (ops IntRegs:$dst),
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def FBU : FPBranchV8<0b0111, (ops brtarget:$dst),
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"fbu $dst",
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[(V8brfcc IntRegs:$dst, SETUO, FCC)]>;
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def FBG : FPBranchV8<0b0110, (ops IntRegs:$dst),
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[(V8brfcc bb:$dst, SETUO, FCC)]>;
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def FBG : FPBranchV8<0b0110, (ops brtarget:$dst),
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"fbg $dst",
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[(V8brfcc IntRegs:$dst, SETGT, FCC)]>;
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def FBUG : FPBranchV8<0b0101, (ops IntRegs:$dst),
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[(V8brfcc bb:$dst, SETGT, FCC)]>;
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def FBUG : FPBranchV8<0b0101, (ops brtarget:$dst),
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"fbug $dst",
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[(V8brfcc IntRegs:$dst, SETUGT, FCC)]>;
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def FBL : FPBranchV8<0b0100, (ops IntRegs:$dst),
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[(V8brfcc bb:$dst, SETUGT, FCC)]>;
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def FBL : FPBranchV8<0b0100, (ops brtarget:$dst),
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"fbl $dst",
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[(V8brfcc IntRegs:$dst, SETLT, FCC)]>;
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def FBUL : FPBranchV8<0b0011, (ops IntRegs:$dst),
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[(V8brfcc bb:$dst, SETLT, FCC)]>;
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def FBUL : FPBranchV8<0b0011, (ops brtarget:$dst),
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"fbul $dst",
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[(V8brfcc IntRegs:$dst, SETULT, FCC)]>;
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def FBLG : FPBranchV8<0b0010, (ops IntRegs:$dst),
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[(V8brfcc bb:$dst, SETULT, FCC)]>;
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def FBLG : FPBranchV8<0b0010, (ops brtarget:$dst),
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"fblg $dst",
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[(V8brfcc IntRegs:$dst, SETONE, FCC)]>;
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def FBNE : FPBranchV8<0b0001, (ops IntRegs:$dst),
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[(V8brfcc bb:$dst, SETONE, FCC)]>;
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def FBNE : FPBranchV8<0b0001, (ops brtarget:$dst),
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"fbne $dst",
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[(V8brfcc IntRegs:$dst, SETNE, FCC)]>;
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def FBE : FPBranchV8<0b1001, (ops IntRegs:$dst),
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[(V8brfcc bb:$dst, SETNE, FCC)]>;
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def FBE : FPBranchV8<0b1001, (ops brtarget:$dst),
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"fbe $dst",
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[(V8brfcc IntRegs:$dst, SETEQ, FCC)]>;
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def FBUE : FPBranchV8<0b1010, (ops IntRegs:$dst),
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[(V8brfcc bb:$dst, SETEQ, FCC)]>;
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def FBUE : FPBranchV8<0b1010, (ops brtarget:$dst),
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"fbue $dst",
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[(V8brfcc IntRegs:$dst, SETUEQ, FCC)]>;
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def FBGE : FPBranchV8<0b1011, (ops IntRegs:$dst),
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[(V8brfcc bb:$dst, SETUEQ, FCC)]>;
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def FBGE : FPBranchV8<0b1011, (ops brtarget:$dst),
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"fbge $dst",
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[(V8brfcc IntRegs:$dst, SETGE, FCC)]>;
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def FBUGE: FPBranchV8<0b1100, (ops IntRegs:$dst),
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[(V8brfcc bb:$dst, SETGE, FCC)]>;
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def FBUGE: FPBranchV8<0b1100, (ops brtarget:$dst),
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"fbuge $dst",
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[(V8brfcc IntRegs:$dst, SETUGE, FCC)]>;
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def FBLE : FPBranchV8<0b1101, (ops IntRegs:$dst),
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[(V8brfcc bb:$dst, SETUGE, FCC)]>;
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def FBLE : FPBranchV8<0b1101, (ops brtarget:$dst),
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"fble $dst",
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[(V8brfcc IntRegs:$dst, SETLE, FCC)]>;
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def FBULE: FPBranchV8<0b1110, (ops IntRegs:$dst),
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[(V8brfcc bb:$dst, SETLE, FCC)]>;
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def FBULE: FPBranchV8<0b1110, (ops brtarget:$dst),
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"fbule $dst",
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[(V8brfcc IntRegs:$dst, SETULE, FCC)]>;
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def FBO : FPBranchV8<0b1111, (ops IntRegs:$dst),
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[(V8brfcc bb:$dst, SETULE, FCC)]>;
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def FBO : FPBranchV8<0b1111, (ops brtarget:$dst),
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"fbo $dst",
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[(V8brfcc IntRegs:$dst, SETO, FCC)]>;
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[(V8brfcc bb:$dst, SETO, FCC)]>;
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@ -68,12 +68,16 @@ def MEMri : Operand<i32> {
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let MIOperandInfo = (ops IntRegs, i32imm);
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}
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// Branch targets have OtherVT type.
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def brtarget : Operand<OtherVT>;
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def SDTV8cmpicc :
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SDTypeProfile<1, 2, [SDTCisVT<0, FlagVT>, SDTCisInt<1>, SDTCisSameAs<1, 2>]>;
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def SDTV8cmpfcc :
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SDTypeProfile<1, 2, [SDTCisVT<0, FlagVT>, SDTCisFP<1>, SDTCisSameAs<1, 2>]>;
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def SDTV8brcc :
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SDTypeProfile<0, 3, [SDTCisInt<0>, SDTCisVT<1, OtherVT>, SDTCisVT<2, FlagVT>]>;
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SDTypeProfile<0, 3, [SDTCisVT<0, OtherVT>, SDTCisVT<1, OtherVT>,
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SDTCisVT<2, FlagVT>]>;
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def V8cmpicc : SDNode<"V8ISD::CMPICC", SDTV8cmpicc>;
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def V8cmpfcc : SDNode<"V8ISD::CMPFCC", SDTV8cmpfcc>;
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@ -410,38 +414,39 @@ class BranchV8<bits<4> cc, dag ops, string asmstr, list<dag> pattern>
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}
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let isBarrier = 1 in
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def BA : BranchV8<0b1000, (ops IntRegs:$dst),
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"ba $dst", []>;
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def BNE : BranchV8<0b1001, (ops IntRegs:$dst),
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def BA : BranchV8<0b1000, (ops brtarget:$dst),
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"ba $dst",
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[(br bb:$dst)]>;
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def BNE : BranchV8<0b1001, (ops brtarget:$dst),
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"bne $dst",
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[(V8bricc IntRegs:$dst, SETNE, ICC)]>;
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def BE : BranchV8<0b0001, (ops IntRegs:$dst),
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[(V8bricc bb:$dst, SETNE, ICC)]>;
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def BE : BranchV8<0b0001, (ops brtarget:$dst),
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"be $dst",
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[(V8bricc IntRegs:$dst, SETEQ, ICC)]>;
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def BG : BranchV8<0b1010, (ops IntRegs:$dst),
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[(V8bricc bb:$dst, SETEQ, ICC)]>;
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def BG : BranchV8<0b1010, (ops brtarget:$dst),
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"bg $dst",
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[(V8bricc IntRegs:$dst, SETGT, ICC)]>;
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def BLE : BranchV8<0b0010, (ops IntRegs:$dst),
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[(V8bricc bb:$dst, SETGT, ICC)]>;
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def BLE : BranchV8<0b0010, (ops brtarget:$dst),
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"ble $dst",
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[(V8bricc IntRegs:$dst, SETLE, ICC)]>;
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def BGE : BranchV8<0b1011, (ops IntRegs:$dst),
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[(V8bricc bb:$dst, SETLE, ICC)]>;
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def BGE : BranchV8<0b1011, (ops brtarget:$dst),
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"bge $dst",
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[(V8bricc IntRegs:$dst, SETGE, ICC)]>;
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def BL : BranchV8<0b0011, (ops IntRegs:$dst),
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[(V8bricc bb:$dst, SETGE, ICC)]>;
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def BL : BranchV8<0b0011, (ops brtarget:$dst),
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"bl $dst",
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[(V8bricc IntRegs:$dst, SETLT, ICC)]>;
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def BGU : BranchV8<0b1100, (ops IntRegs:$dst),
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[(V8bricc bb:$dst, SETLT, ICC)]>;
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def BGU : BranchV8<0b1100, (ops brtarget:$dst),
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"bgu $dst",
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[(V8bricc IntRegs:$dst, SETUGT, ICC)]>;
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def BLEU : BranchV8<0b0100, (ops IntRegs:$dst),
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[(V8bricc bb:$dst, SETUGT, ICC)]>;
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def BLEU : BranchV8<0b0100, (ops brtarget:$dst),
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"bleu $dst",
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[(V8bricc IntRegs:$dst, SETULE, ICC)]>;
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def BCC : BranchV8<0b1101, (ops IntRegs:$dst),
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[(V8bricc bb:$dst, SETULE, ICC)]>;
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def BCC : BranchV8<0b1101, (ops brtarget:$dst),
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"bcc $dst",
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[(V8bricc IntRegs:$dst, SETUGE, ICC)]>;
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def BCS : BranchV8<0b0101, (ops IntRegs:$dst),
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[(V8bricc bb:$dst, SETUGE, ICC)]>;
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def BCS : BranchV8<0b0101, (ops brtarget:$dst),
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"bcs $dst",
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[(V8bricc IntRegs:$dst, SETULT, ICC)]>;
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[(V8bricc bb:$dst, SETULT, ICC)]>;
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// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121
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@ -453,48 +458,48 @@ class FPBranchV8<bits<4> cc, dag ops, string asmstr, list<dag> pattern>
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let hasDelaySlot = 1;
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}
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def FBU : FPBranchV8<0b0111, (ops IntRegs:$dst),
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def FBU : FPBranchV8<0b0111, (ops brtarget:$dst),
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"fbu $dst",
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[(V8brfcc IntRegs:$dst, SETUO, FCC)]>;
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def FBG : FPBranchV8<0b0110, (ops IntRegs:$dst),
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[(V8brfcc bb:$dst, SETUO, FCC)]>;
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def FBG : FPBranchV8<0b0110, (ops brtarget:$dst),
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"fbg $dst",
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[(V8brfcc IntRegs:$dst, SETGT, FCC)]>;
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def FBUG : FPBranchV8<0b0101, (ops IntRegs:$dst),
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[(V8brfcc bb:$dst, SETGT, FCC)]>;
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def FBUG : FPBranchV8<0b0101, (ops brtarget:$dst),
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"fbug $dst",
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[(V8brfcc IntRegs:$dst, SETUGT, FCC)]>;
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def FBL : FPBranchV8<0b0100, (ops IntRegs:$dst),
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[(V8brfcc bb:$dst, SETUGT, FCC)]>;
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def FBL : FPBranchV8<0b0100, (ops brtarget:$dst),
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"fbl $dst",
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[(V8brfcc IntRegs:$dst, SETLT, FCC)]>;
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def FBUL : FPBranchV8<0b0011, (ops IntRegs:$dst),
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[(V8brfcc bb:$dst, SETLT, FCC)]>;
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def FBUL : FPBranchV8<0b0011, (ops brtarget:$dst),
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"fbul $dst",
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[(V8brfcc IntRegs:$dst, SETULT, FCC)]>;
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def FBLG : FPBranchV8<0b0010, (ops IntRegs:$dst),
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[(V8brfcc bb:$dst, SETULT, FCC)]>;
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def FBLG : FPBranchV8<0b0010, (ops brtarget:$dst),
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"fblg $dst",
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[(V8brfcc IntRegs:$dst, SETONE, FCC)]>;
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def FBNE : FPBranchV8<0b0001, (ops IntRegs:$dst),
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[(V8brfcc bb:$dst, SETONE, FCC)]>;
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def FBNE : FPBranchV8<0b0001, (ops brtarget:$dst),
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"fbne $dst",
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[(V8brfcc IntRegs:$dst, SETNE, FCC)]>;
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def FBE : FPBranchV8<0b1001, (ops IntRegs:$dst),
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[(V8brfcc bb:$dst, SETNE, FCC)]>;
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def FBE : FPBranchV8<0b1001, (ops brtarget:$dst),
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"fbe $dst",
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[(V8brfcc IntRegs:$dst, SETEQ, FCC)]>;
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def FBUE : FPBranchV8<0b1010, (ops IntRegs:$dst),
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[(V8brfcc bb:$dst, SETEQ, FCC)]>;
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def FBUE : FPBranchV8<0b1010, (ops brtarget:$dst),
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"fbue $dst",
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[(V8brfcc IntRegs:$dst, SETUEQ, FCC)]>;
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def FBGE : FPBranchV8<0b1011, (ops IntRegs:$dst),
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[(V8brfcc bb:$dst, SETUEQ, FCC)]>;
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def FBGE : FPBranchV8<0b1011, (ops brtarget:$dst),
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"fbge $dst",
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[(V8brfcc IntRegs:$dst, SETGE, FCC)]>;
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def FBUGE: FPBranchV8<0b1100, (ops IntRegs:$dst),
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[(V8brfcc bb:$dst, SETGE, FCC)]>;
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def FBUGE: FPBranchV8<0b1100, (ops brtarget:$dst),
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"fbuge $dst",
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[(V8brfcc IntRegs:$dst, SETUGE, FCC)]>;
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def FBLE : FPBranchV8<0b1101, (ops IntRegs:$dst),
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[(V8brfcc bb:$dst, SETUGE, FCC)]>;
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def FBLE : FPBranchV8<0b1101, (ops brtarget:$dst),
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"fble $dst",
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[(V8brfcc IntRegs:$dst, SETLE, FCC)]>;
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def FBULE: FPBranchV8<0b1110, (ops IntRegs:$dst),
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[(V8brfcc bb:$dst, SETLE, FCC)]>;
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def FBULE: FPBranchV8<0b1110, (ops brtarget:$dst),
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"fbule $dst",
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[(V8brfcc IntRegs:$dst, SETULE, FCC)]>;
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def FBO : FPBranchV8<0b1111, (ops IntRegs:$dst),
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[(V8brfcc bb:$dst, SETULE, FCC)]>;
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def FBO : FPBranchV8<0b1111, (ops brtarget:$dst),
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"fbo $dst",
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[(V8brfcc IntRegs:$dst, SETO, FCC)]>;
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[(V8brfcc bb:$dst, SETO, FCC)]>;
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