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[SystemZ] Implement isLegalAddressingMode()
The loop optimizers were assuming that scales > 1 were OK. I think this is actually a bug in TargetLoweringBase::isLegalAddressingMode(), since it seems to be trying to reject anything that isn't r+i or r+r, but it has no default case for scales other than 0, 1 or 2. Implementing the hook for z means that z can no longer test any change there though. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187497 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -290,6 +290,21 @@ bool SystemZTargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
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return true;
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return true;
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}
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}
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bool SystemZTargetLowering::isLegalAddressingMode(const AddrMode &AM,
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Type *Ty) const {
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// Punt on globals for now, although they can be used in limited
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// RELATIVE LONG cases.
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if (AM.BaseGV)
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return false;
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// Require a 20-bit signed offset.
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if (!isInt<20>(AM.BaseOffs))
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return false;
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// Indexing is OK but no scale factor can be applied.
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return AM.Scale == 0 || AM.Scale == 1;
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}
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Inline asm support
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// Inline asm support
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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@ -126,12 +126,15 @@ public:
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virtual MVT getScalarShiftAmountTy(EVT LHSTy) const LLVM_OVERRIDE {
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virtual MVT getScalarShiftAmountTy(EVT LHSTy) const LLVM_OVERRIDE {
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return MVT::i32;
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return MVT::i32;
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}
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}
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virtual EVT getSetCCResultType(LLVMContext &, EVT) const {
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virtual EVT getSetCCResultType(LLVMContext &, EVT) const LLVM_OVERRIDE {
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return MVT::i32;
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return MVT::i32;
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}
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}
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virtual bool isFMAFasterThanFMulAndFAdd(EVT VT) const LLVM_OVERRIDE;
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virtual bool isFMAFasterThanFMulAndFAdd(EVT VT) const LLVM_OVERRIDE;
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virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
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virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const LLVM_OVERRIDE;
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virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const;
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virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const
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LLVM_OVERRIDE;
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virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const
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LLVM_OVERRIDE;
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virtual const char *getTargetNodeName(unsigned Opcode) const LLVM_OVERRIDE;
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virtual const char *getTargetNodeName(unsigned Opcode) const LLVM_OVERRIDE;
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virtual std::pair<unsigned, const TargetRegisterClass *>
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virtual std::pair<unsigned, const TargetRegisterClass *>
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getRegForInlineAsmConstraint(const std::string &Constraint,
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getRegForInlineAsmConstraint(const std::string &Constraint,
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25
test/CodeGen/SystemZ/loop-01.ll
Normal file
25
test/CodeGen/SystemZ/loop-01.ll
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@ -0,0 +1,25 @@
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; Test loop tuning.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
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; Test that strength reduction is applied to addresses with a scale factor,
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; but that indexed addressing can still be used.
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define void @f1(i32 *%dest, i32 %a) {
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; CHECK-LABEL: f1
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; CHECK-NOT: sllg
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; CHECK: st %r3, 0({{%r[1-5],%r[1-5]}})
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; CHECK: br %r14
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entry:
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br label %loop
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loop:
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%index = phi i64 [ 0, %entry ], [ %next, %loop ]
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%ptr = getelementptr i32 *%dest, i64 %index
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store i32 %a, i32 *%ptr
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%next = add i64 %index, 1
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%cmp = icmp ne i64 %next, 100
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br i1 %cmp, label %loop, label %exit
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exit:
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ret void
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}
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