mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-05 13:09:10 +00:00
Add an indirect branch pattern for ARM. Testcase will be coming soon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85355 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
b235224ee7
commit
04ea6e5150
@ -657,6 +657,16 @@ let isReturn = 1, isTerminator = 1, isBarrier = 1 in
|
||||
let Inst{27-20} = 0b00010010;
|
||||
}
|
||||
|
||||
// Indirect branches
|
||||
let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
|
||||
def BRIND : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx $dst",
|
||||
[(brind GPR:$dst)]> {
|
||||
let Inst{7-4} = 0b0001;
|
||||
let Inst{19-8} = 0b111111111111;
|
||||
let Inst{27-20} = 0b00010010;
|
||||
}
|
||||
}
|
||||
|
||||
// FIXME: remove when we have a way to marking a MI with these properties.
|
||||
// FIXME: Should pc be an implicit operand like PICADD, etc?
|
||||
let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
|
||||
|
Loading…
Reference in New Issue
Block a user