mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-23 02:29:18 +00:00
ARM: provide a new generic hint intrinsic
Introduce the llvm.arm.hint(i32) intrinsic that can be used to inject hints into the instruction stream. This is particularly useful for generating IR from a compiler where the user may inject an intrinsic (e.g. __yield). These are then pattern substituted into the correct instruction which already existed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207242 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
5d71d87bff
commit
04f826c062
@ -123,6 +123,7 @@ def int_arm_crc32cw : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
|
|||||||
//===----------------------------------------------------------------------===//
|
//===----------------------------------------------------------------------===//
|
||||||
// HINT
|
// HINT
|
||||||
def int_arm_sevl : Intrinsic<[], []>;
|
def int_arm_sevl : Intrinsic<[], []>;
|
||||||
|
def int_arm_hint : Intrinsic<[], [llvm_i32_ty]>;
|
||||||
|
|
||||||
//===----------------------------------------------------------------------===//
|
//===----------------------------------------------------------------------===//
|
||||||
// Advanced SIMD (NEON)
|
// Advanced SIMD (NEON)
|
||||||
|
@ -1827,7 +1827,8 @@ PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
|
|||||||
}
|
}
|
||||||
|
|
||||||
def HINT : AI<(outs), (ins imm0_239:$imm), MiscFrm, NoItinerary,
|
def HINT : AI<(outs), (ins imm0_239:$imm), MiscFrm, NoItinerary,
|
||||||
"hint", "\t$imm", []>, Requires<[IsARM, HasV6]> {
|
"hint", "\t$imm", [(int_arm_hint imm0_239:$imm)]>,
|
||||||
|
Requires<[IsARM, HasV6]> {
|
||||||
bits<8> imm;
|
bits<8> imm;
|
||||||
let Inst{27-8} = 0b00110010000011110000;
|
let Inst{27-8} = 0b00110010000011110000;
|
||||||
let Inst{7-0} = imm;
|
let Inst{7-0} = imm;
|
||||||
|
@ -269,7 +269,8 @@ class T1SystemEncoding<bits<8> opc>
|
|||||||
let Inst{7-0} = opc;
|
let Inst{7-0} = opc;
|
||||||
}
|
}
|
||||||
|
|
||||||
def tHINT : T1pI<(outs), (ins imm0_15:$imm), NoItinerary, "hint", "\t$imm", []>,
|
def tHINT : T1pI<(outs), (ins imm0_15:$imm), NoItinerary, "hint", "\t$imm",
|
||||||
|
[(int_arm_hint imm0_15:$imm)]>,
|
||||||
T1SystemEncoding<0x00>,
|
T1SystemEncoding<0x00>,
|
||||||
Requires<[IsThumb, HasV6M]> {
|
Requires<[IsThumb, HasV6M]> {
|
||||||
bits<4> imm;
|
bits<4> imm;
|
||||||
|
@ -3671,7 +3671,8 @@ def : t2InstAlias<"cps.w $mode", (t2CPS1p imm0_31:$mode), 0>;
|
|||||||
|
|
||||||
// A6.3.4 Branches and miscellaneous control
|
// A6.3.4 Branches and miscellaneous control
|
||||||
// Table A6-14 Change Processor State, and hint instructions
|
// Table A6-14 Change Processor State, and hint instructions
|
||||||
def t2HINT : T2I<(outs), (ins imm0_239:$imm), NoItinerary, "hint", ".w\t$imm",[]> {
|
def t2HINT : T2I<(outs), (ins imm0_239:$imm), NoItinerary, "hint", ".w\t$imm",
|
||||||
|
[(int_arm_hint imm0_239:$imm)]> {
|
||||||
bits<8> imm;
|
bits<8> imm;
|
||||||
let Inst{31-3} = 0b11110011101011111000000000000;
|
let Inst{31-3} = 0b11110011101011111000000000000;
|
||||||
let Inst{7-0} = imm;
|
let Inst{7-0} = imm;
|
||||||
|
69
test/CodeGen/ARM/hints.ll
Normal file
69
test/CodeGen/ARM/hints.ll
Normal file
@ -0,0 +1,69 @@
|
|||||||
|
; RUN: llc -mtriple armv7-eabi -o - %s | FileCheck %s
|
||||||
|
; RUN: llc -mtriple thumbv6m-eabi -o - %s | FileCheck %s
|
||||||
|
; RUN: llc -mtriple thumbv7-eabi -o - %s | FileCheck %s
|
||||||
|
|
||||||
|
declare void @llvm.arm.hint(i32) nounwind
|
||||||
|
|
||||||
|
define void @hint_nop() {
|
||||||
|
entry:
|
||||||
|
tail call void @llvm.arm.hint(i32 0) nounwind
|
||||||
|
ret void
|
||||||
|
}
|
||||||
|
|
||||||
|
; CHECK-LABEL: hint_nop
|
||||||
|
; CHECK: nop
|
||||||
|
|
||||||
|
define void @hint_yield() {
|
||||||
|
entry:
|
||||||
|
tail call void @llvm.arm.hint(i32 1) nounwind
|
||||||
|
ret void
|
||||||
|
}
|
||||||
|
|
||||||
|
; CHECK-LABEL: hint_yield
|
||||||
|
; CHECK: yield
|
||||||
|
|
||||||
|
define void @hint_wfe() {
|
||||||
|
entry:
|
||||||
|
tail call void @llvm.arm.hint(i32 2) nounwind
|
||||||
|
ret void
|
||||||
|
}
|
||||||
|
|
||||||
|
; CHECK-LABEL: hint_wfe
|
||||||
|
; CHECK: wfe
|
||||||
|
|
||||||
|
define void @hint_wfi() {
|
||||||
|
entry:
|
||||||
|
tail call void @llvm.arm.hint(i32 3) nounwind
|
||||||
|
ret void
|
||||||
|
}
|
||||||
|
|
||||||
|
; CHECK-LABEL: hint_wfi
|
||||||
|
; CHECK: wfi
|
||||||
|
|
||||||
|
define void @hint_sev() {
|
||||||
|
entry:
|
||||||
|
tail call void @llvm.arm.hint(i32 4) nounwind
|
||||||
|
ret void
|
||||||
|
}
|
||||||
|
|
||||||
|
; CHECK-LABEL: hint_sev
|
||||||
|
; CHECK: sev
|
||||||
|
|
||||||
|
define void @hint_sevl() {
|
||||||
|
entry:
|
||||||
|
tail call void @llvm.arm.hint(i32 5) nounwind
|
||||||
|
ret void
|
||||||
|
}
|
||||||
|
|
||||||
|
; CHECK-LABEL: hint_sevl
|
||||||
|
; CHECK: hint #5
|
||||||
|
|
||||||
|
define void @hint_undefined() {
|
||||||
|
entry:
|
||||||
|
tail call void @llvm.arm.hint(i32 8) nounwind
|
||||||
|
ret void
|
||||||
|
}
|
||||||
|
|
||||||
|
; CHECK-LABEL: hint_undefined
|
||||||
|
; CHECK: hint #8
|
||||||
|
|
Loading…
Reference in New Issue
Block a user